| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 186 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in R600TargetLowering()
188 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Expand); in R600TargetLowering()
189 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Expand); in R600TargetLowering()
192 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); in R600TargetLowering()
193 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Expand); in R600TargetLowering()
194 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Expand); in R600TargetLowering()
197 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in R600TargetLowering()
198 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Expand); in R600TargetLowering()
199 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Expand); in R600TargetLowering()
201 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); in R600TargetLowering()
[all …]
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| D | AMDGPUISelLowering.cpp | 1130 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG); in LowerOperation()
1167 case ISD::SIGN_EXTEND_INREG: in ReplaceNodeResults()
1624 Div = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Div, InRegSize); in LowerDIVREM24()
1625 Rem = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Rem, InRegSize); in LowerDIVREM24()
2773 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp); in LowerSIGN_EXTEND_INREG()
4051 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom, in PerformDAGCombine()
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| D | SIISelLowering.cpp | 228 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom); in SITargetLowering()
229 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom); in SITargetLowering()
230 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom); in SITargetLowering()
231 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom); in SITargetLowering()
232 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom); in SITargetLowering()
233 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v3i16, Custom); in SITargetLowering()
234 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom); in SITargetLowering()
235 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Custom); in SITargetLowering()
740 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG); in SITargetLowering()
7319 Cvt = DAG.getNode(ISD::SIGN_EXTEND_INREG, SL, MVT::i32, NewLoad, in widenLoad()
[all …]
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| D | AMDGPUISelDAGToDAG.cpp | 895 case ISD::SIGN_EXTEND_INREG: in Select()
2009 case ISD::SIGN_EXTEND_INREG: { in SelectS_BFE()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 117 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in BPFTargetLowering()
118 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); in BPFTargetLowering()
119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in BPFTargetLowering()
120 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand); in BPFTargetLowering()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 214 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in WebAssemblyTargetLowering()
219 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Action); in WebAssemblyTargetLowering()
222 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Expand); in WebAssemblyTargetLowering()
972 case ISD::SIGN_EXTEND_INREG: in ReplaceNodeResults()
1024 case ISD::SIGN_EXTEND_INREG: in LowerOperation()
1301 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Op.getValueType(), in LowerSIGN_EXTEND_INREG()
1341 if (IndexExt->getOpcode() != ISD::SIGN_EXTEND_INREG) in LowerBUILD_VECTOR()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 547 SIGN_EXTEND_INREG, enumerator
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLoweringHVX.cpp | 137 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Custom); in initializeHVXLowering()
199 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Legal); in initializeHVXLowering()
202 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Legal); in initializeHVXLowering()
1077 Elems[i] = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NTy, in LowerHvxConcatVectors()
1465 if (Op.getOpcode() == ISD::SIGN_EXTEND_INREG) { in SplitHvxPairOp()
1555 case ISD::SIGN_EXTEND_INREG: in LowerHvxOperation()
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| D | HexagonISelDAGToDAG.cpp | 1453 case ISD::SIGN_EXTEND_INREG: { in DetectUseSxtw()
1521 case ISD::SIGN_EXTEND_INREG: in keepsLowBits()
1597 if (N->getOpcode() == ISD::SIGN_EXTEND_INREG) { in isPositiveHalfWord()
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| D | HexagonISelLowering.cpp | 1352 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in HexagonTargetLowering()
1530 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Legal); in HexagonTargetLowering()
1531 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Legal); in HexagonTargetLowering()
1532 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal); in HexagonTargetLowering()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/ |
| D | ARCISelLowering.cpp | 138 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Custom); in ARCTargetLowering()
757 case ISD::SIGN_EXTEND_INREG: in LowerOperation()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiISelLowering.cpp | 130 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in LanaiTargetLowering()
131 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); in LanaiTargetLowering()
132 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in LanaiTargetLowering()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 87 case ISD::SIGN_EXTEND_INREG: in PromoteIntegerResult()
578 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, in PromoteIntRes_INT_EXTEND()
867 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, in PromoteIntRes_SADDSUBO()
954 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), in PromoteIntRes_SIGN_EXTEND_INREG()
1164 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(), in PromoteIntRes_XMULO()
1563 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), in PromoteIntOp_SIGN_EXTEND()
1828 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break; in ExpandIntegerResult()
3441 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, in ExpandIntRes_SIGN_EXTEND()
3455 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo, in ExpandIntRes_SIGN_EXTEND_INREG()
3467 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, in ExpandIntRes_SIGN_EXTEND_INREG()
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| D | LegalizeTypes.h | 254 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), Op, in SExtPromotedInteger()
275 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Op.getValueType(), Op, in SExtOrZExtPromotedInteger()
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| D | LegalizeVectorOps.cpp | 438 case ISD::SIGN_EXTEND_INREG: in LegalizeOp()
848 case ISD::SIGN_EXTEND_INREG: in Expand()
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| D | SelectionDAGDumper.cpp | 322 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; in getOperationName()
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| D | LegalizeDAG.cpp | 759 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, in LegalizeLoadOps()
932 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, in LegalizeLoadOps()
1024 case ISD::SIGN_EXTEND_INREG: { in LegalizeOp()
2833 RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, OuterType, in ExpandNode()
2927 case ISD::SIGN_EXTEND_INREG: { in ExpandNode()
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| D | SelectionDAG.cpp | 2194 case ISD::SIGN_EXTEND_INREG: in GetDemandedBits()
2953 case ISD::SIGN_EXTEND_INREG: { in computeKnownBits()
3636 case ISD::SIGN_EXTEND_INREG: in ComputeNumSignBits()
5278 case ISD::SIGN_EXTEND_INREG: { in getNode()
5467 case ISD::SIGN_EXTEND_INREG: in getNode()
7456 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && in getNode()
9309 case ISD::SIGN_EXTEND_INREG: { in UnrollVectorOp()
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| D | DAGCombiner.cpp | 1146 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) in SExtPromoteOperand()
1158 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, NewOp.getValueType(), NewOp, in SExtPromoteOperand()
1564 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); in visit()
2480 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) { in visitADDLikeCommutative()
3238 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) { in visitSUB()
7737 TLI.getOperationAction(ISD::SIGN_EXTEND_INREG, ExtVT) == in visitSRA()
7739 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, in visitSRA()
9654 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, in visitSIGN_EXTEND()
9660 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Op, in visitSIGN_EXTEND()
10373 if (Opc == ISD::SIGN_EXTEND_INREG) { in ReduceLoadWidth()
[all …]
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| D | LegalizeVectorTypes.cpp | 59 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break; in ScalarizeVectorResult()
466 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), CondVT, in ScalarizeVecRes_VSELECT()
839 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break; in SplitVectorResult()
2695 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break; in WidenVectorResult()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in MSP430TargetLowering()
990 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT, Victim, in LowerShifts()
1246 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT, in LowerSIGN_EXTEND()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 405 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i64, Legal); in NVPTXTargetLowering()
406 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); in NVPTXTargetLowering()
407 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal); in NVPTXTargetLowering()
408 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); in NVPTXTargetLowering()
409 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in NVPTXTargetLowering()
4586 Op.getOpcode() == ISD::SIGN_EXTEND_INREG) { in IsMulWideOperandDemotable()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 489 N.getOpcode() == ISD::SIGN_EXTEND_INREG) { in getExtendTypeForNode()
491 if (N.getOpcode() == ISD::SIGN_EXTEND_INREG) in getExtendTypeForNode()
1665 assert(N->getOpcode() == ISD::SIGN_EXTEND_INREG); in isBitfieldExtractOpFromSExtInReg()
1880 case ISD::SIGN_EXTEND_INREG: in isBitfieldExtractOp()
3076 case ISD::SIGN_EXTEND_INREG: in Select()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 200 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in PPCTargetLowering()
411 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in PPCTargetLowering()
669 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand); in PPCTargetLowering()
959 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Legal); in PPCTargetLowering()
960 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Legal); in PPCTargetLowering()
961 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Legal); in PPCTargetLowering()
962 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Legal); in PPCTargetLowering()
963 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Legal); in PPCTargetLowering()
964 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal); in PPCTargetLowering()
965 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal); in PPCTargetLowering()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1490 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in SparcTargetLowering()
1491 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); in SparcTargetLowering()
1492 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); in SparcTargetLowering()
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