| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | EarlyIfConversion.cpp | 113 unsigned TReg, FReg; member
118 : PHI(phi), TReg(0), FReg(0), CondCycles(0), TCycles(0), FCycles(0) {} in PHIInfo()
515 PI.TReg = PI.PHI->getOperand(i).getReg(); in canConvertIf()
519 assert(Register::isVirtualRegister(PI.TReg) && "Bad PHI"); in canConvertIf()
523 if (!TII->canInsertSelect(*Head, Cond, PI.TReg, PI.FReg, in canConvertIf()
571 TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg); in replacePHIInstrs()
592 if (PI.TReg == PI.FReg) { in rewritePHIOperands()
595 DstReg = PI.TReg; in rewritePHIOperands()
600 DstReg, Cond, PI.TReg, PI.FReg); in rewritePHIOperands()
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringMIPS32.cpp | 2115 Variable *TReg = Target->makeReg(IceType_i32, Target->getReservedTmpReg()); in legalizeImmediate() local
2118 Target->_lui(TReg, Target->Ctx->getConstantInt32(UpperBits)); in legalizeImmediate()
2119 Target->_ori(Reg, TReg, LowerBits); in legalizeImmediate()
3017 auto *TReg = makeReg(IceType_i32); in lowerAssign() local
3018 _mov(TReg, SCont); in lowerAssign()
3019 _mov(DCont, TReg); in lowerAssign()
3866 Variable *TReg = makeReg(DestTy); in lowerExtractElement() local
3896 _srl(TReg, SrcE, 8); in lowerExtractElement()
3897 _andi(TDest, TReg, 0xff); in lowerExtractElement()
3900 _srl(TReg, SrcE, 16); in lowerExtractElement()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.cpp | 588 Register TReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass); in insertSelect() local
590 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), TReg).addReg(TrueReg); in insertSelect()
592 TrueReg = TReg; in insertSelect()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMAsmPrinter.cpp | 1335 Register TReg = MI->getOperand(0).getReg(); in EmitInstruction() local
1338 if (TIP.first == TReg) { in EmitInstruction()
1346 ThumbIndirectPads.push_back(std::make_pair(TReg, TRegSym)); in EmitInstruction()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 4752 unsigned TReg = Inst.getOperand(2).getReg(); in expandRotation() local
4766 TOut.emitRRR(Mips::SUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI); in expandRotation()
4772 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TReg, Inst.getLoc(), STI); in expandRotation()
4797 TOut.emitRRR(Mips::SUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), STI); in expandRotation()
4799 TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI); in expandRotation()
4877 unsigned TReg = Inst.getOperand(2).getReg(); in expandDRotation() local
4891 TOut.emitRRR(Mips::DSUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI); in expandDRotation()
4897 TOut.emitRRR(Mips::DROTRV, DReg, SReg, TReg, Inst.getLoc(), STI); in expandDRotation()
4922 TOut.emitRRR(Mips::DSUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), STI); in expandDRotation()
4924 TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI); in expandDRotation()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstructionSelector.cpp | 2261 const Register TReg = I.getOperand(2).getReg(); in select() local
2276 .addUse(TReg) in select()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 32129 Register TReg = MRI->createVirtualRegister(&X86::GR64RegClass); in EmitSjLjDispatchBlock() local
32141 BuildMI(DispContBB, DL, TII->get(X86::ADD64rr), TReg) in EmitSjLjDispatchBlock()
32145 BuildMI(DispContBB, DL, TII->get(X86::JMP64r)).addReg(TReg); in EmitSjLjDispatchBlock()
|