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Searched refs:TSFlags (Results 1 – 25 of 88) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIInstrInfo.h334 return MI.getDesc().TSFlags & SIInstrFlags::SALU; in isSALU()
338 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU()
342 return MI.getDesc().TSFlags & SIInstrFlags::VALU; in isVALU()
346 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU()
358 return MI.getDesc().TSFlags & SIInstrFlags::SOP1; in isSOP1()
362 return get(Opcode).TSFlags & SIInstrFlags::SOP1; in isSOP1()
366 return MI.getDesc().TSFlags & SIInstrFlags::SOP2; in isSOP2()
370 return get(Opcode).TSFlags & SIInstrFlags::SOP2; in isSOP2()
374 return MI.getDesc().TSFlags & SIInstrFlags::SOPC; in isSOPC()
378 return get(Opcode).TSFlags & SIInstrFlags::SOPC; in isSOPC()
[all …]
DSIInstrFormats.td131 let TSFlags{0} = SALU;
132 let TSFlags{1} = VALU;
134 let TSFlags{2} = SOP1;
135 let TSFlags{3} = SOP2;
136 let TSFlags{4} = SOPC;
137 let TSFlags{5} = SOPK;
138 let TSFlags{6} = SOPP;
140 let TSFlags{7} = VOP1;
141 let TSFlags{8} = VOP2;
142 let TSFlags{9} = VOPC;
[all …]
DR600InstrFormats.td53 let TSFlags{4} = Trig;
54 let TSFlags{5} = Op3;
58 let TSFlags{6} = isVector;
59 let TSFlags{8-7} = FlagOperandIdx;
60 let TSFlags{9} = HasNativeOperands;
61 let TSFlags{10} = Op1;
62 let TSFlags{11} = Op2;
63 let TSFlags{12} = VTXInst;
64 let TSFlags{13} = TEXInst;
65 let TSFlags{14} = ALUInst;
[all …]
DR600Defines.h61 #define IS_VTX(desc) ((desc).TSFlags & R600_InstFlag::VTX_INST)
62 #define IS_TEX(desc) ((desc).TSFlags & R600_InstFlag::TEX_INST)
DR600OptimizeVectorRegisters.cpp153 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST) in canSwizzle()
267 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST) in SwizzleInput()
352 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST) { in runOnMachineFunction()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonInstrFormats.td71 let TSFlags{6-0} = Type.Value;
75 let TSFlags{7} = isSolo;
78 let TSFlags{8} = isSoloAX;
81 let TSFlags{9} = isRestrictSlot1AOK;
85 let TSFlags{10} = isPredicated;
87 let TSFlags{11} = isPredicatedFalse;
89 let TSFlags{12} = isPredicatedNew;
91 let TSFlags{13} = isPredicateLate; // Late predicate producer insn.
95 let TSFlags{14} = isNewValue; // New-value consumer insn.
97 let TSFlags{15} = hasNewValue; // New-value producer insn.
[all …]
DHexagonInstrFormatsV5.td51 let TSFlags{6-0} = Type.Value;
55 let TSFlags{7} = isPredicated;
57 let TSFlags{8} = isPredicatedFalse;
59 let TSFlags{9} = isPredicatedNew;
63 let TSFlags{10} = isNewValue; // New-value consumer insn.
65 let TSFlags{11} = hasNewValue; // New-value producer insn.
67 let TSFlags{14-12} = opNewValue; // New-value produced operand.
69 let TSFlags{15} = isNVStorable; // Store that can become new-value store.
71 let TSFlags{16} = isNVStore; // New-value store insn.
75 let TSFlags{17} = isExtendable; // Insn may be extended.
[all …]
DHexagonInstrInfo.cpp1558 const uint64_t F = MI.getDesc().TSFlags; in isPredicated()
2007 const uint64_t F = MI.getDesc().TSFlags; in isAccumulator()
2031 const uint64_t F = MI.getDesc().TSFlags; in isConstExtended()
2179 const uint64_t F = MID.TSFlags; in isExtendable()
2201 const uint64_t F = MI.getDesc().TSFlags; in isExtended()
2214 const uint64_t F = get(Opcode).TSFlags; in isFloat()
2401 const uint64_t F = MI.getDesc().TSFlags; in isNewValue()
2406 const uint64_t F = get(Opcode).TSFlags; in isNewValue()
2423 const uint64_t F = MI.getDesc().TSFlags; in isNewValueStore()
2428 const uint64_t F = get(Opcode).TSFlags; in isNewValueStore()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp110 uint64_t TSFlags, bool Rex, unsigned &CurByte,
114 void emitPrefixImpl(uint64_t TSFlags, unsigned &CurOp, unsigned &CurByte,
118 void emitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
125 bool emitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
129 uint8_t determineREXPrefix(const MCInst &MI, uint64_t TSFlags, int MemOperand,
141 static bool isCDisp8(uint64_t TSFlags, int Value, int &CValue) { in isCDisp8() argument
142 assert(((TSFlags & X86II::EncodingMask) == X86II::EVEX) && in isCDisp8()
146 (TSFlags & X86II::CD8_Scale_Mask) >> X86II::CD8_Scale_Shift; in isCDisp8()
166 static MCFixupKind getImmFixupKind(uint64_t TSFlags) { in getImmFixupKind() argument
167 unsigned Size = X86II::getSizeOfImm(TSFlags); in getImmFixupKind()
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DX86ATTInstPrinter.cpp102 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) { in printVecCompareInstr()
103 if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS) in printVecCompareInstr()
105 else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD) in printVecCompareInstr()
160 unsigned CurOp = (Desc.TSFlags & X86II::EVEX_K) ? 3 : 2; in printVecCompareInstr()
162 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) { in printVecCompareInstr()
163 if (Desc.TSFlags & X86II::EVEX_B) { in printVecCompareInstr()
166 if (Desc.TSFlags & X86II::VEX_W) in printVecCompareInstr()
173 if (Desc.TSFlags & X86II::EVEX_L2) in printVecCompareInstr()
174 NumElts = (Desc.TSFlags & X86II::VEX_W) ? 8 : 16; in printVecCompareInstr()
175 else if (Desc.TSFlags & X86II::VEX_L) in printVecCompareInstr()
[all …]
DX86IntelInstPrinter.cpp85 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) { in printVecCompareInstr()
86 if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS) in printVecCompareInstr()
88 else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD) in printVecCompareInstr()
142 if (Desc.TSFlags & X86II::EVEX_K) { in printVecCompareInstr()
152 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) { in printVecCompareInstr()
153 if (Desc.TSFlags & X86II::EVEX_B) { in printVecCompareInstr()
156 if (Desc.TSFlags & X86II::VEX_W) in printVecCompareInstr()
163 if (Desc.TSFlags & X86II::EVEX_L2) in printVecCompareInstr()
164 NumElts = (Desc.TSFlags & X86II::VEX_W) ? 8 : 16; in printVecCompareInstr()
165 else if (Desc.TSFlags & X86II::VEX_L) in printVecCompareInstr()
[all …]
DX86BaseInfo.h905 inline uint8_t getBaseOpcodeFor(uint64_t TSFlags) { in getBaseOpcodeFor() argument
906 return TSFlags >> X86II::OpcodeShift; in getBaseOpcodeFor()
909 inline bool hasImm(uint64_t TSFlags) { in hasImm() argument
910 return (TSFlags & X86II::ImmMask) != 0; in hasImm()
915 inline unsigned getSizeOfImm(uint64_t TSFlags) { in getSizeOfImm() argument
916 switch (TSFlags & X86II::ImmMask) { in getSizeOfImm()
932 inline bool isImmPCRel(uint64_t TSFlags) { in isImmPCRel() argument
933 switch (TSFlags & X86II::ImmMask) { in isImmPCRel()
951 inline bool isImmSigned(uint64_t TSFlags) { in isImmSigned() argument
952 switch (TSFlags & X86II::ImmMask) { in isImmSigned()
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DX86InstPrinterCommon.cpp324 uint64_t TSFlags = Desc.TSFlags; in printInstFlags() local
327 if ((TSFlags & X86II::LOCK) || (Flags & X86::IP_HAS_LOCK)) in printInstFlags()
330 if ((TSFlags & X86II::NOTRACK) || (Flags & X86::IP_HAS_NOTRACK)) in printInstFlags()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/
DNVPTXInstrFormats.td49 let TSFlags{3-0} = VecInstType;
50 let TSFlags{4-4} = IsSimpleMove;
51 let TSFlags{5-5} = IsLoad;
52 let TSFlags{6-6} = IsStore;
53 let TSFlags{7} = IsTex;
54 let TSFlags{9-8} = IsSuld;
55 let TSFlags{10} = IsSust;
56 let TSFlags{11} = IsSurfTexQuery;
57 let TSFlags{12} = IsTexModeUnified;
DNVPTXReplaceImageHandles.cpp83 if (MCID.TSFlags & NVPTXII::IsTexFlag) { in processInstr()
89 if (!(MCID.TSFlags & NVPTXII::IsTexModeUnifiedFlag)) { in processInstr()
95 } else if (MCID.TSFlags & NVPTXII::IsSuldMask) { in processInstr()
97 1 << (((MCID.TSFlags & NVPTXII::IsSuldMask) >> NVPTXII::IsSuldShift) - 1); in processInstr()
105 } else if (MCID.TSFlags & NVPTXII::IsSustFlag) { in processInstr()
112 } else if (MCID.TSFlags & NVPTXII::IsSurfTexQueryFlag) { in processInstr()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCInstrInfo.cpp211 uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getMemAccessSize()
218 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getAddrMode()
286 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtendableOp()
304 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentAlignment()
310 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentBits()
316 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in isExtentSigned()
349 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getNewValueOp()
374 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getNewValueOp2()
393 const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags; in getType()
463 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in hasNewValue()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrFMA3Info.cpp132 const X86InstrFMA3Group *llvm::getFMA3Group(unsigned Opcode, uint64_t TSFlags) { in getFMA3Group() argument
135 uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); in getFMA3Group()
136 bool IsFMA3 = ((TSFlags & X86II::EncodingMask) == X86II::VEX || in getFMA3Group()
137 (TSFlags & X86II::EncodingMask) == X86II::EVEX) && in getFMA3Group()
138 (TSFlags & X86II::OpMapMask) == X86II::T8 && in getFMA3Group()
139 (TSFlags & X86II::OpPrefixMask) == X86II::PD && in getFMA3Group()
149 if (TSFlags & X86II::EVEX_RC) in getFMA3Group()
151 else if (TSFlags & X86II::EVEX_B) in getFMA3Group()
DX86EvexToVex.cpp222 if ((Desc.TSFlags & X86II::EncodingMask) != X86II::EVEX) in CompressEvexToVexImpl()
228 if (Desc.TSFlags & (X86II::EVEX_K | X86II::EVEX_B)) in CompressEvexToVexImpl()
233 if (Desc.TSFlags & X86II::EVEX_L2) in CompressEvexToVexImpl()
252 (Desc.TSFlags & X86II::VEX_L) ? makeArrayRef(X86EvexToVex256CompressTable) in CompressEvexToVexImpl()
DX86InstrFormats.td344 // TSFlags layout should be kept in sync with X86BaseInfo.h.
345 let TSFlags{6-0} = FormBits;
346 let TSFlags{8-7} = OpSizeBits;
347 let TSFlags{10-9} = AdSizeBits;
349 let TSFlags{12-11} = OpPrefixBits{1-0};
350 let TSFlags{15-13} = OpMapBits;
351 let TSFlags{16} = hasREX_WPrefix;
352 let TSFlags{20-17} = ImmT.Value;
353 let TSFlags{23-21} = FPForm.Value;
354 let TSFlags{24} = hasLockPrefix;
[all …]
DX86InstrFMA3Info.h97 const X86InstrFMA3Group *getFMA3Group(unsigned Opcode, uint64_t TSFlags);
DX86OptimizeLEAs.cpp346 int MemOpNo = X86II::getMemoryOperandNo(Desc.TSFlags) + in chooseBestLEA()
449 int MemOpNo = X86II::getMemoryOperandNo(Desc.TSFlags); in isReplaceable()
515 int MemOpNo = X86II::getMemoryOperandNo(Desc.TSFlags); in removeRedundantAddrCalc()
645 X86II::getMemoryOperandNo(Desc.TSFlags) + in removeRedundantLEAs()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMHazardRecognizer.cpp22 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; in hasRAWHazard()
43 if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) { in getHazardType()
53 (LastMCID.TSFlags & ARMII::DomainMask) == ARMII::DomainGeneral) { in getHazardType()
DARMBaseRegisterInfo.cpp500 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); in getFrameIndexInstrOffset()
686 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); in isFrameOffsetLegal()
799 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 || in eliminateFrameIndex()
800 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6 || in eliminateFrameIndex()
801 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrModeT2_i7 || in eliminateFrameIndex()
802 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrModeT2_i7s2 || in eliminateFrameIndex()
803 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == in eliminateFrameIndex()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCHazardRecognizers.cpp287 uint64_t TSFlags = MCID.TSFlags; in GetInstrType() local
289 isFirst = TSFlags & PPCII::PPC970_First; in GetInstrType()
290 isSingle = TSFlags & PPCII::PPC970_Single; in GetInstrType()
291 isCracked = TSFlags & PPCII::PPC970_Cracked; in GetInstrType()
292 return (PPCII::PPC970_Unit)(TSFlags & PPCII::PPC970_Mask); in GetInstrType()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/MCTargetDesc/
DR600MCCodeEmitter.cpp149 ((Desc.TSFlags & R600_InstFlag::OP1) || in encodeInstruction()
150 Desc.TSFlags & R600_InstFlag::OP2)) { in encodeInstruction()
176 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags)) in getMachineOpValue()

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