/third_party/openssl/crypto/bn/asm/ |
D | ppc.pl | 120 $UMULL= "mullw"; # unsigned multiply low 144 $UMULL= "mulld"; # unsigned multiply low 296 $UMULL r9,r5,r5 305 $UMULL r7,r5,r6 319 $UMULL r7,r6,r6 326 $UMULL r7,r5,r6 339 $UMULL r7,r5,r6 351 $UMULL r7,r5,r6 362 $UMULL r7,r6,r6 369 $UMULL r7,r5,r6 [all …]
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D | ppc-mont.pl | 62 $UMULL= "mullw"; # unsigned multiply low 83 $UMULL= "mulld"; # unsigned multiply low 178 $UMULL $lo0,$aj,$m0 ; ap[0]*bp[0] 184 $UMULL $m1,$lo0,$n0 ; "tp[0]"*n0 186 $UMULL $alo,$aj,$m0 ; ap[1]*bp[0] 189 $UMULL $lo1,$nj,$m1 ; np[0]*m1 195 $UMULL $nlo,$nj,$m1 ; np[1]*m1 206 $UMULL $alo,$aj,$m0 ; ap[j]*bp[0] 210 $UMULL $nlo,$nj,$m1 ; np[j]*m1 241 $UMULL $lo0,$aj,$m0 ; ap[0]*bp[i] [all …]
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
D | ARMGenMCPseudoLowering.inc | 256 TmpInst.setOpcode(ARM::UMULL);
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D | ARMGenAsmWriter.inc | 2564 3223278U, // UMULL 6788 33554432U, // UMULL 11451 case ARM::UMULL: 11555 case ARM::UMULL:
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D | ARMGenSubtargetInfo.inc | 5171 { 1, 10, 11, 459, 462 }, // 339 UMULL 6218 { 1, 63, 65, 2237, 2241 }, // 339 UMULL 7265 { 1, 283, 284, 5235, 5239 }, // 339 UMULL 11087 {DBGFIELD("UMULL") 1, false, false, 15, 2, 15, 2, 0, 0}, // #339 12536 {DBGFIELD("UMULL") 2, false, false, 24, 1, 550, 2, 64, 2}, // #339 13985 {DBGFIELD("UMULL") 2, false, false, 13, 1, 12, 2, 64, 2}, // #339 15434 {DBGFIELD("UMULL") 1, false, false, 111, 1, 9, 1, 64, 3}, // #339 16883 {DBGFIELD("UMULL") 3, false, false, 173, 2, 57, 2, 0, 0}, // #339
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D | ARMGenMCCodeEmitter.inc | 1872 UINT64_C(8388752), // UMULL 15171 case ARM::UMULL: { 18547 CEFBS_IsARM_HasV6, // UMULL = 1859
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D | ARMGenAsmMatcher.inc | 11510 …{ 1791 /* umull */, ARM::UMULL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AM… 11511 …{ 1791 /* umull */, ARM::UMULL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AM…
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D | ARMGenInstrInfo.inc | 1874 UMULL = 1859, 4589 UMULL = 339, 7705 …::HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #1859 = UMULL
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D | ARMGenDisassemblerTables.inc | 125 /* 293 */ MCD::OPC_Decode, 195, 14, 6, // Opcode: UMULL
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D | ARMGenDAGISel.inc | 48067 /*104310*/ OPC_MorphNodeTo2, TARGET_VAL(ARM::UMULL), 0, 48070 // Dst: (UMULL:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
D | AArch64ISelLowering.h | 196 UMULL, enumerator
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D | AArch64ISelLowering.cpp | 1370 case AArch64ISD::UMULL: return "AArch64ISD::UMULL"; in getTargetNodeName() 2891 NewOpc = AArch64ISD::UMULL; in LowerMUL() 2899 NewOpc = AArch64ISD::UMULL; in LowerMUL() 2903 NewOpc = AArch64ISD::UMULL; in LowerMUL()
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D | AArch64InstrInfo.td | 524 def AArch64umull : SDNode<"AArch64ISD::UMULL", SDT_AArch64mull>; 4515 defm UMULL : SIMDLongThreeVectorBHS<1, 0b1100, "umull", int_aarch64_neon_umull>; 4521 // Additional patterns for SMULL and UMULL 5647 defm UMULL : SIMDVectorIndexedLongSD<1, 0b1010, "umull",
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/third_party/pcre2/pcre2/src/sljit/ |
D | sljitNativeARM_T2_32.c | 186 #define UMULL 0xfba00000 macro 1480 return push_inst32(compiler, (op == SLJIT_LMUL_UW ? UMULL : SMULL) in sljit_emit_op0()
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D | sljitNativeARM_32.c | 116 #define UMULL 0xe0800090 macro 1946 return push_inst(compiler, (op == SLJIT_LMUL_UW ? UMULL : SMULL) in sljit_emit_op0()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
D | ARMScheduleSwift.td | 281 (instregex "SMULL$", "UMULL$", "t2SMULL$", "t2UMULL$")>;
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D | ARMScheduleR52.td | 278 "SMULL$", "UMULL$", "t2SMULL$", "t2UMULL$",
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D | ARMScheduleA57.td | 298 // Multiply long: SMULL, UMULL
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D | ARMInstrInfo.td | 4170 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi), 4193 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 6178 // MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but 6198 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
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D | ARMScheduleA9.td | 2551 (instregex "SMULL", "SMULLv5", "UMULL", "UMULLv5", "SMLAL$", "UMLAL",
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
D | AArch64GenFastISel.inc | 6282 // FastEmit functions for AArch64ISD::UMULL. 9803 …case AArch64ISD::UMULL: return fastEmit_AArch64ISD_UMULL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsK…
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