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Searched refs:VECREDUCE_FMIN (Results 1 – 10 of 10) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DISDOpcodes.h933 VECREDUCE_FMAX, VECREDUCE_FMIN, enumerator
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp486 case ISD::VECREDUCE_FMIN: in LegalizeOp()
990 case ISD::VECREDUCE_FMIN: in Expand()
DSelectionDAGDumper.cpp450 case ISD::VECREDUCE_FMIN: return "vecreduce_fmin"; in getOperationName()
DLegalizeVectorTypes.cpp616 case ISD::VECREDUCE_FMIN: in ScalarizeVectorOperand()
1996 case ISD::VECREDUCE_FMIN: in SplitVectorOperand()
2084 case ISD::VECREDUCE_FMIN: in SplitVecOp_VECREDUCE()
4237 case ISD::VECREDUCE_FMIN: in WidenVectorOperand()
4721 case ISD::VECREDUCE_FMIN: in WidenVecOp_VECREDUCE()
DLegalizeDAG.cpp1160 case ISD::VECREDUCE_FMIN: in LegalizeOp()
3809 case ISD::VECREDUCE_FMIN: in ExpandNode()
DTargetLowering.cpp7625 case ISD::VECREDUCE_FMIN: in expandVecReduce()
DSelectionDAGBuilder.cpp9011 Res = DAG.getNode(ISD::VECREDUCE_FMIN, dl, VT, Op1); in visitVectorReduce()
DDAGCombiner.cpp1625 case ISD::VECREDUCE_FMIN: return visitVECREDUCE(N); in visit()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DTargetLoweringBase.cpp724 setOperationAction(ISD::VECREDUCE_FMIN, VT, Expand); in initActions()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp798 setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom); in AArch64TargetLowering()
3274 case ISD::VECREDUCE_FMIN: in LowerOperation()
8564 case ISD::VECREDUCE_FMIN: { in LowerVECREDUCE()