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Searched refs:ZReg (Results 1 – 7 of 7) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp3881 static inline bool isMatchingOrAlias(unsigned ZReg, unsigned Reg) { in isMatchingOrAlias() argument
3882 assert((ZReg >= AArch64::Z0) && (ZReg <= AArch64::Z31)); in isMatchingOrAlias()
3883 return (ZReg == ((Reg - AArch64::B0) + AArch64::Z0)) || in isMatchingOrAlias()
3884 (ZReg == ((Reg - AArch64::H0) + AArch64::Z0)) || in isMatchingOrAlias()
3885 (ZReg == ((Reg - AArch64::S0) + AArch64::Z0)) || in isMatchingOrAlias()
3886 (ZReg == ((Reg - AArch64::D0) + AArch64::Z0)) || in isMatchingOrAlias()
3887 (ZReg == ((Reg - AArch64::Q0) + AArch64::Z0)) || in isMatchingOrAlias()
3888 (ZReg == ((Reg - AArch64::Z0) + AArch64::Z0)); in isMatchingOrAlias()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstructionSelector.cpp3275 Register ZReg = Is32Bit ? AArch64::WZR : AArch64::XZR; in emitCMN() local
3277 auto CmpMI = MIRBuilder.buildInstr(Opc, {ZReg}, {LHS.getReg()}); in emitCMN()
3299 Register ZReg = Is32Bit ? AArch64::WZR : AArch64::XZR; in emitTST() local
3307 auto TstMI = MIRBuilder.buildInstr(Opc, {ZReg}, {LHS}); in emitTST()
3333 Register ZReg; in emitIntegerCompare() local
3340 ZReg = AArch64::WZR; in emitIntegerCompare()
3343 ZReg = AArch64::XZR; in emitIntegerCompare()
3353 auto CmpMI = MIRBuilder.buildInstr(CmpOpc).addDef(ZReg).addUse(LHS.getReg()); in emitIntegerCompare()
DAArch64FastISel.cpp560 unsigned ZReg = Is64Bit ? AArch64::XZR : AArch64::WZR; in fastMaterializeFloatZero() local
562 return fastEmitInst_r(Opc, TLI.getRegClassFor(VT), ZReg, /*IsKill=*/true); in fastMaterializeFloatZero()
4048 unsigned Opc, ZReg; in emitMul_rr() local
4055 Opc = AArch64::MADDWrrr; ZReg = AArch64::WZR; break; in emitMul_rr()
4057 Opc = AArch64::MADDXrrr; ZReg = AArch64::XZR; break; in emitMul_rr()
4063 /*IsKill=*/ZReg, true); in emitMul_rr()
DAArch64InstrInfo.cpp462 unsigned ZReg = removeCopies(MRI, DefMI->getOperand(1).getReg()); in canFoldIntoCSel() local
463 if (ZReg != AArch64::XZR && ZReg != AArch64::WZR) in canFoldIntoCSel()
480 unsigned ZReg = removeCopies(MRI, DefMI->getOperand(1).getReg()); in canFoldIntoCSel() local
481 if (ZReg != AArch64::XZR && ZReg != AArch64::WZR) in canFoldIntoCSel()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagon.td28 "Hexagon ZReg extension instructions">;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrInfo.cpp4142 unsigned ZReg = in expandPostRAPseudo() local
4144 MIB->getOperand(0).setReg(ZReg); in expandPostRAPseudo()
DX86ISelLowering.cpp31496 Register ZReg = MRI.createVirtualRegister(PtrRC); in emitSetJmpShadowStackFix() local
31499 .addDef(ZReg) in emitSetJmpShadowStackFix()
31500 .addReg(ZReg, RegState::Undef) in emitSetJmpShadowStackFix()
31501 .addReg(ZReg, RegState::Undef); in emitSetJmpShadowStackFix()
31506 BuildMI(*MBB, MI, DL, TII->get(RdsspOpc), SSPCopyReg).addReg(ZReg); in emitSetJmpShadowStackFix()
31746 Register ZReg = MRI.createVirtualRegister(PtrRC); in emitLongJmpShadowStackFix() local
31749 .addDef(ZReg) in emitLongJmpShadowStackFix()
31750 .addReg(ZReg, RegState::Undef) in emitLongJmpShadowStackFix()
31751 .addReg(ZReg, RegState::Undef); in emitLongJmpShadowStackFix()
31756 BuildMI(checkSspMBB, DL, TII->get(RdsspOpc), SSPCopyReg).addReg(ZReg); in emitLongJmpShadowStackFix()