| /third_party/mesa3d/src/amd/vulkan/ |
| D | radv_nir_apply_pipeline_layout.c | 33 uint32_t address32_hi; member
52 return nir_pack_64_2x32_split(b, ptr, nir_imm_int(b, state->address32_hi)); in convert_pointer_to_64_bit()
175 return nir_vec4(b, rsrc, nir_imm_int(b, S_008F04_BASE_ADDRESS_HI(state->address32_hi)), in load_inline_buffer_descriptor()
534 .address32_hi = device->physical_device->rad_info.address32_hi, in radv_nir_apply_pipeline_layout()
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| D | si_cmd_buffer.c | 85 S_00B834_DATA(device->physical_device->rad_info.address32_hi >> 8)); in si_emit_compute()
319 S_00B524_MEM_BASE(device->physical_device->rad_info.address32_hi >> 8)); in si_emit_graphics()
321 S_00B324_MEM_BASE(device->physical_device->rad_info.address32_hi >> 8)); in si_emit_graphics()
324 S_00B414_MEM_BASE(device->physical_device->rad_info.address32_hi >> 8)); in si_emit_graphics()
326 S_00B214_MEM_BASE(device->physical_device->rad_info.address32_hi >> 8)); in si_emit_graphics()
329 S_00B524_MEM_BASE(device->physical_device->rad_info.address32_hi >> 8)); in si_emit_graphics()
331 S_00B324_MEM_BASE(device->physical_device->rad_info.address32_hi >> 8)); in si_emit_graphics()
336 S_00B124_MEM_BASE(device->physical_device->rad_info.address32_hi >> 8)); in si_emit_graphics()
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| D | radv_aco_shader_info.h | 169 ASSIGN_FIELD(address32_hi); in radv_aco_convert_opts()
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| D | radv_shader.c | 2219 options->address32_hi = device->physical_device->rad_info.address32_hi;
2432 options.address32_hi = device->physical_device->rad_info.address32_hi;
2494 options.address32_hi = device->physical_device->rad_info.address32_hi;
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| D | radv_shader.h | 133 uint32_t address32_hi; member
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| D | radv_nir_to_llvm.c | 93 if (options->address32_hi) { in create_llvm_function()
95 options->address32_hi); in create_llvm_function()
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| D | radv_private.h | 1793 assert(va == 0 || (va >> 32) == device->physical_device->rad_info.address32_hi); in radv_emit_shader_pointer_body()
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| /third_party/mesa3d/src/amd/compiler/ |
| D | aco_shader_info.h | 195 uint32_t address32_hi; member
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| D | aco_instruction_selection.cpp | 837 Operand::c32((unsigned)ctx->options->address32_hi)); in convert_pointer_to_64_bit()
12353 if (options->address32_hi >= 0xffff8000 || options->address32_hi <= 0x7fff) { in select_vs_prolog()
12355 options->address32_hi & 0xFFFF); in select_vs_prolog()
12358 Operand::c32((unsigned)options->address32_hi)); in select_vs_prolog()
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| /third_party/mesa3d/src/amd/vulkan/winsys/null/ |
| D | radv_null_winsys.c | 148 info->address32_hi = info->gfx_level >= GFX9 ? 0xffff8000u : 0x0; in radv_null_winsys_query_info()
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| /third_party/mesa3d/src/amd/common/ |
| D | ac_gpu_info.h | 135 uint32_t address32_hi; member
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| D | ac_gpu_info.c | 724 r = amdgpu_query_sw_info(dev, amdgpu_sw_info_address32_hi, &info->address32_hi); in ac_query_gpu_info()
1495 fprintf(f, " address32_hi = 0x%x\n", info->address32_hi); in ac_print_gpu_info()
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| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_buffer.c | 193 assert((start >> 32) == sscreen->info.address32_hi); in si_alloc_resource()
194 assert((last >> 32) == sscreen->info.address32_hi); in si_alloc_resource()
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| D | si_build_pm4.h | 298 assert((va) == 0 || ((va) >> 32) == sscreen->info.address32_hi); \
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| D | si_shader_llvm_resources.c | 70 desc1 = LLVMConstInt(ctx->ac.i32, S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0); in load_const_buffer_desc_fast_path()
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| D | si_shader_llvm.c | 186 if (ctx->screen->info.address32_hi) { in si_llvm_create_func()
188 ctx->screen->info.address32_hi); in si_llvm_create_func()
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| D | si_state_shaders.cpp | 743 S_00B424_MEM_BASE(sscreen->info.address32_hi >> 8)); in si_shader_hs()
818 S_00B324_MEM_BASE(sscreen->info.address32_hi >> 8)); in si_shader_es()
1151 S_00B224_MEM_BASE(sscreen->info.address32_hi >> 8)); in si_shader_gs()
1733 S_00B124_MEM_BASE(sscreen->info.address32_hi >> 8)); in si_shader_vs()
2008 S_00B024_MEM_BASE(sscreen->info.address32_hi >> 8)); in si_shader_ps()
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| D | si_state.c | 5681 S_00B524_MEM_BASE(sscreen->info.address32_hi >> 8)); in si_init_cs_preamble_state()
5683 S_00B324_MEM_BASE(sscreen->info.address32_hi >> 8)); in si_init_cs_preamble_state()
5686 S_00B414_MEM_BASE(sscreen->info.address32_hi >> 8)); in si_init_cs_preamble_state()
5688 S_00B214_MEM_BASE(sscreen->info.address32_hi >> 8)); in si_init_cs_preamble_state()
5691 S_00B524_MEM_BASE(sscreen->info.address32_hi >> 8)); in si_init_cs_preamble_state()
5934 assert((sscreen->attribute_ring->gpu_address >> 32) == sscreen->info.address32_hi); in si_init_cs_preamble_state()
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| D | si_shader_llvm_tess.c | 246 desc[1] = LLVMConstInt(ctx->ac.i32, S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0); in get_tess_ring_descriptor()
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| D | si_compute.c | 380 S_00B834_DATA(sctx->screen->info.address32_hi >> 8)); in si_emit_initial_compute_regs()
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| D | si_shader_llvm_vs.c | 768 LLVMConstInt(ctx->ac.i32, S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi) | in si_llvm_build_vs_exports()
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| D | si_descriptors.c | 174 assert((desc->buffer->gpu_address >> 32) == sctx->screen->info.address32_hi); in si_upload_descriptors()
175 assert((desc->gpu_address >> 32) == sctx->screen->info.address32_hi); in si_upload_descriptors()
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| D | si_pipe.c | 1074 sscreen->info.address32_hi); in si_disk_cache_create()
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