| /third_party/pcre2/pcre2/src/sljit/ |
| D | sljitNativeARM_64.c | 867 sljit_s32 arg, sljit_sw argw, sljit_s32 tmp_reg) in emit_op_mem() argument
878 argw &= 0x3; in emit_op_mem()
880 if (argw == 0 || argw == shift) in emit_op_mem()
882 | RN(arg & REG_MASK) | RM(OFFS_REG(arg)) | (argw ? (1 << 12) : 0)); in emit_op_mem()
884 …t(compiler, ADD | RD(tmp_reg) | RN(arg & REG_MASK) | RM(OFFS_REG(arg)) | ((sljit_ins)argw << 10))); in emit_op_mem()
891 FAIL_IF(load_immediate(compiler, tmp_reg, argw & ~(0xfff << shift))); in emit_op_mem()
893 argw = (argw >> shift) & 0xfff; in emit_op_mem()
895 return push_inst(compiler, STRBI | type | RT(reg) | RN(tmp_reg) | ((sljit_ins)argw << 10)); in emit_op_mem()
898 if (argw >= 0 && (argw & ((1 << shift) - 1)) == 0) { in emit_op_mem()
899 if ((argw >> shift) <= 0xfff) in emit_op_mem()
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| D | sljitNativeARM_32.c | 1674 sljit_s32 arg, sljit_sw argw, sljit_s32 tmp_reg) in emit_op_mem() argument
1684 FAIL_IF(load_immediate(compiler, tmp_reg, (sljit_uw)argw & ~(sljit_uw)0xfff)); in emit_op_mem()
1685 argw &= 0xfff; in emit_op_mem()
1688 FAIL_IF(load_immediate(compiler, tmp_reg, (sljit_uw)argw & ~(sljit_uw)0xff)); in emit_op_mem()
1689 argw &= 0xff; in emit_op_mem()
1693 is_type1_transfer ? argw : TYPE2_TRANSFER_IMM(argw))); in emit_op_mem()
1699 argw &= 0x3; in emit_op_mem()
1701 if (argw != 0 && !is_type1_transfer) { in emit_op_mem()
1702 …FAIL_IF(push_inst(compiler, ADD | RD(tmp_reg) | RN(arg) | RM(offset_reg) | ((sljit_uw)argw << 7))); in emit_op_mem()
1708 RM(offset_reg) | (is_type1_transfer ? (1 << 25) : 0) | ((sljit_uw)argw << 7))); in emit_op_mem()
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| D | sljitNativeSPARC_common.c | 693 …fast(struct sljit_compiler *compiler, sljit_u32 flags, sljit_s32 reg, sljit_s32 arg, sljit_sw argw) in getput_arg_fast() argument
697 if ((!(arg & OFFS_REG_MASK) && argw <= SIMM_MAX && argw >= SIMM_MIN) in getput_arg_fast()
698 || ((arg & OFFS_REG_MASK) && (argw & 0x3) == 0)) { in getput_arg_fast()
704 | S1(arg & REG_MASK) | ((arg & OFFS_REG_MASK) ? S2(OFFS_REG(arg)) : IMM(argw)), in getput_arg_fast()
714 static sljit_s32 can_cache(sljit_s32 arg, sljit_sw argw, sljit_s32 next_arg, sljit_sw next_argw) in can_cache() argument
720 argw &= 0x3; in can_cache()
721 SLJIT_ASSERT(argw); in can_cache()
723 if ((arg & OFFS_REG_MASK) == (next_arg & OFFS_REG_MASK) && argw == next_argw) in can_cache()
728 if (((next_argw - argw) <= SIMM_MAX && (next_argw - argw) >= SIMM_MIN)) in can_cache()
734 …mpiler *compiler, sljit_u32 flags, sljit_s32 reg, sljit_s32 arg, sljit_sw argw, sljit_s32 next_arg… in getput_arg() argument
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| D | sljitNativeMIPS_common.c | 758 …(struct sljit_compiler *compiler, sljit_s32 flags, sljit_s32 reg_ar, sljit_s32 arg, sljit_sw argw);
1122 …t(struct sljit_compiler *compiler, sljit_s32 flags, sljit_s32 reg_ar, sljit_s32 arg, sljit_sw argw) in getput_arg_fast() argument
1126 if (!(arg & OFFS_REG_MASK) && argw <= SIMM_MAX && argw >= SIMM_MIN) { in getput_arg_fast()
1131 …| TA(reg_ar) | IMM(argw), ((flags & MEM_MASK) <= GPR_REG && (flags & LOAD_DATA)) ? reg_ar : MOVABL… in getput_arg_fast()
1140 static sljit_s32 can_cache(sljit_s32 arg, sljit_sw argw, sljit_s32 next_arg, sljit_sw next_argw) in can_cache() argument
1146 argw &= 0x3; in can_cache()
1148 …if (argw && argw == next_argw && (arg == next_arg || (arg & OFFS_REG_MASK) == (next_arg & OFFS_REG… in can_cache()
1154 if (((next_argw - argw) <= SIMM_MAX && (next_argw - argw) >= SIMM_MIN)) in can_cache()
1163 …ler *compiler, sljit_s32 flags, sljit_s32 reg_ar, sljit_s32 arg, sljit_sw argw, sljit_s32 next_arg… in getput_arg() argument
1184 argw &= 0x3; in getput_arg()
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| D | sljitNativeARM_T2_32.c | 894 #define OFFSET_CHECK(imm, shift) (!(argw & ~(imm << shift)))
990 sljit_s32 arg, sljit_sw argw, sljit_s32 tmp_reg) in emit_op_mem() argument
1000 tmp = get_imm((sljit_uw)argw & ~(sljit_uw)0xfff); in emit_op_mem()
1003 …return push_inst32(compiler, sljit_mem32[flags] | MEM_IMM12 | RT4(reg) | RN4(tmp_reg) | (argw & 0x… in emit_op_mem()
1006 FAIL_IF(load_immediate(compiler, tmp_reg, (sljit_uw)argw)); in emit_op_mem()
1013 argw &= 0x3; in emit_op_mem()
1017 if (!argw && IS_3_LO_REGS(reg, arg, other_r)) in emit_op_mem()
1019 …inst32(compiler, sljit_mem32[flags] | RT4(reg) | RN4(arg) | RM4(other_r) | ((sljit_ins)argw << 4)); in emit_op_mem()
1022 if (argw > 0xfff) { in emit_op_mem()
1023 tmp = get_imm((sljit_uw)argw & ~(sljit_uw)0xfff); in emit_op_mem()
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| D | sljitNativePPC_common.c | 1065 sljit_s32 arg, sljit_sw argw, sljit_s32 tmp_reg) in emit_op_mem() argument
1076 argw &= 0x3; in emit_op_mem()
1079 if (argw != 0) { in emit_op_mem()
1081 …ler, RLWINM | S(OFFS_REG(arg)) | A(tmp_reg) | ((sljit_ins)argw << 11) | ((31 - (sljit_ins)argw) <<… in emit_op_mem()
1083 FAIL_IF(push_inst(compiler, RLDI(tmp_reg, OFFS_REG(arg), argw, 63 - argw, 1))); in emit_op_mem()
1101 if ((inst & INT_ALIGNED) && (argw & 0x3) != 0) { in emit_op_mem()
1102 FAIL_IF(load_immediate(compiler, tmp_reg, argw)); in emit_op_mem()
1109 if (argw <= SIMM_MAX && argw >= SIMM_MIN) in emit_op_mem()
1110 return push_inst(compiler, INST_CODE_AND_DST(inst, inp_flags, reg) | A(arg) | IMM(argw)); in emit_op_mem()
1113 if (argw <= 0x7fff7fffl && argw >= -0x80000000l) { in emit_op_mem()
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| D | sljitNativeX86_common.c | 691 #define BINARY_IMM32(op_imm, immw, arg, argw) \ argument
693 inst = emit_x86_instruction(compiler, 1 | EX86_BIN_INS, SLJIT_IMM, immw, arg, argw); \
700 #define BINARY_IMM(op_imm, op_mr, immw, arg, argw) \ argument
703 BINARY_IMM32(op_imm, immw, arg, argw); \
707 … inst = emit_x86_instruction(compiler, 1, (arg == TMP_REG1) ? TMP_REG2 : TMP_REG1, 0, arg, argw); \
718 #define BINARY_IMM(op_imm, op_mr, immw, arg, argw) \ argument
719 BINARY_IMM32(op_imm, immw, arg, argw)
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