| /third_party/mesa3d/src/amd/compiler/ |
| D | aco_lower_to_hw_instr.cpp | 201 unsigned bank_mask, bool bound_ctrl, Operand* identity = NULL) in emit_int64_dpp_op() argument
215 bld.vop1_dpp(aco_opcode::v_mov_b32, vtmp_def[0], src0[0], dpp_ctrl, row_mask, bank_mask, in emit_int64_dpp_op()
220 dpp_ctrl, row_mask, bank_mask, bound_ctrl); in emit_int64_dpp_op()
223 Operand(vcc, bld.lm), dpp_ctrl, row_mask, bank_mask, bound_ctrl); in emit_int64_dpp_op()
225 bld.vop2_dpp(aco_opcode::v_and_b32, dst[0], src0[0], src1[0], dpp_ctrl, row_mask, bank_mask, in emit_int64_dpp_op()
227 bld.vop2_dpp(aco_opcode::v_and_b32, dst[1], src0[1], src1[1], dpp_ctrl, row_mask, bank_mask, in emit_int64_dpp_op()
230 bld.vop2_dpp(aco_opcode::v_or_b32, dst[0], src0[0], src1[0], dpp_ctrl, row_mask, bank_mask, in emit_int64_dpp_op()
232 bld.vop2_dpp(aco_opcode::v_or_b32, dst[1], src0[1], src1[1], dpp_ctrl, row_mask, bank_mask, in emit_int64_dpp_op()
235 bld.vop2_dpp(aco_opcode::v_xor_b32, dst[0], src0[0], src1[0], dpp_ctrl, row_mask, bank_mask, in emit_int64_dpp_op()
237 bld.vop2_dpp(aco_opcode::v_xor_b32, dst[1], src0[1], src1[1], dpp_ctrl, row_mask, bank_mask, in emit_int64_dpp_op()
[all …]
|
| D | aco_opt_value_numbering.cpp | 182 aDPP.bank_mask == bDPP.bank_mask && aDPP.row_mask == bDPP.row_mask && in operator ()()
|
| D | aco_print_ir.cpp | 605 if (dpp.bank_mask != 0xf) in print_instr_format_specific()
606 fprintf(output, " bank_mask:0x%.1x", dpp.bank_mask); in print_instr_format_specific()
|
| D | aco_optimizer_postRA.cpp | 442 assert(mov->dpp16().row_mask == 0xf && mov->dpp16().bank_mask == 0xf); in try_combine_dpp()
|
| D | aco_ir.cpp | 382 dpp->bank_mask = 0xf; in convert_to_DPP()
|
| D | aco_assembler.cpp | 684 encoding |= (0xF & dpp.bank_mask) << 24; in emit_instruction()
|
| D | aco_ir.h | 1447 uint8_t bank_mask : 4; member
|
| D | aco_optimizer.cpp | 1752 assert(instr->dpp16().row_mask == 0xf && instr->dpp16().bank_mask == 0xf); in label_instruction()
2446 new_dpp->bank_mask = cmp_dpp.bank_mask; in combine_inverse_comparison()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | VOP1Instructions.td | 291 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl, FI:$fi);
838 (i32 (int_amdgcn_mov_dpp i32:$src, timm:$dpp_ctrl, timm:$row_mask, timm:$bank_mask,
841 (as_i32imm $row_mask), (as_i32imm $bank_mask),
847 timm:$bank_mask, timm:$bound_ctrl)),
849 (as_i32imm $row_mask), (as_i32imm $bank_mask),
|
| D | GCNDPPCombine.cpp | 252 DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask)); in createDPPInst()
372 auto *BankMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask); in combineDPPMov()
|
| D | VOP2Instructions.td | 294 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
348 let AsmDPP = "$vdst, vcc, $src0, $src1 $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
362 let AsmDPP = "$vdst, vcc, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
382 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
397 let AsmDPP = "$vdst, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
418 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
|
| D | SIInstrInfo.td | 1084 def bank_mask : NamedOperandU32<"BankMask", NamedMatchClass<"BankMask">>;
1749 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl),
1755 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl)
1760 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl)
1769 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl)
1774 row_mask:$row_mask, bank_mask:$bank_mask,
1970 string ret = dst#args#" $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
|
| D | VOPInstructions.td | 578 bits<4> bank_mask;
590 let Inst{59-56} = bank_mask;
|
| D | SIInstructions.td | 1876 (i64 (int_amdgcn_mov_dpp i64:$src, timm:$dpp_ctrl, timm:$row_mask, timm:$bank_mask,
1879 (as_i32imm $row_mask), (as_i32imm $bank_mask),
1885 timm:$bank_mask, timm:$bound_ctrl)),
1887 (as_i32imm $row_mask), (as_i32imm $bank_mask),
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
| D | IntrinsicsAMDGPU.td | 1525 // llvm.amdgcn.mov.dpp.i32 <src> <dpp_ctrl> <row_mask> <bank_mask> <bound_ctrl>
1532 // llvm.amdgcn.update.dpp.i32 <old> <src> <dpp_ctrl> <row_mask> <bank_mask> <bound_ctrl>
1535 // v_mov_b32 <dest> <src> <dpp_ctrl> <row_mask> <bank_mask> <bound_ctrl>
|
| /third_party/mesa3d/src/amd/llvm/ |
| D | ac_llvm_build.c | 3283 enum dpp_ctrl dpp_ctrl, unsigned row_mask, unsigned bank_mask, in _ac_build_dpp() argument
3295 LLVMConstInt(ctx->i32, row_mask, 0), LLVMConstInt(ctx->i32, bank_mask, 0), in _ac_build_dpp()
3303 enum dpp_ctrl dpp_ctrl, unsigned row_mask, unsigned bank_mask, in ac_build_dpp() argument
3321 _ac_build_dpp(ctx, old, src, dpp_ctrl, row_mask, bank_mask, bound_ctrl); in ac_build_dpp()
3326 ret = _ac_build_dpp(ctx, old, src, dpp_ctrl, row_mask, bank_mask, bound_ctrl); in ac_build_dpp()
|