Searched refs:gather4 (Results 1 – 19 of 19) sorted by relevance
150 … sampler MsgDesc: gather4 SIMD4x2 Surface = 1 Sampler = 0 mlen 2 rlen 1 { align16 1Q };226 … sampler MsgDesc: gather4 SIMD4x2 Surface = 3 Sampler = 0 mlen 2 rlen 1 { align16 1Q };228 … sampler MsgDesc: gather4 SIMD4x2 Surface = 4 Sampler = 1 mlen 2 rlen 1 { align16 1Q };230 … sampler MsgDesc: gather4 SIMD4x2 Surface = 5 Sampler = 2 mlen 2 rlen 1 { align16 1Q };276 … sampler MsgDesc: gather4 SIMD8 Surface = 6 Sampler = 0 mlen 3 rlen 4 { align1 1Q };278 … sampler MsgDesc: gather4 SIMD8 Surface = 10 Sampler = 4 mlen 3 rlen 4 { align1 1Q };280 … sampler MsgDesc: gather4 SIMD8 Surface = 7 Sampler = 1 mlen 4 rlen 4 { align1 1Q };282 … sampler MsgDesc: gather4 SIMD8 Surface = 8 Sampler = 2 mlen 4 rlen 4 { align1 1Q };284 … sampler MsgDesc: gather4 SIMD8 Surface = 9 Sampler = 3 mlen 5 rlen 4 { align1 1Q };286 … sampler MsgDesc: gather4 SIMD16 Surface = 6 Sampler = 0 mlen 5 rlen 8 { align1 1H };[all …]
50 … sampler MsgDesc: gather4 SIMD8 Surface = 2 Sampler = 0 mlen 3 rlen 4 { align1 1Q };54 … sampler MsgDesc: gather4 SIMD16 Surface = 2 Sampler = 0 mlen 6 rlen 8 { align1 1H };82 … sampler MsgDesc: gather4 SIMD4x2 Surface = 1 Sampler = 0 mlen 2 rlen 1 { align16 1Q };110 … sampler MsgDesc: gather4 SIMD8 Surface = 2 Sampler = 0 mlen 2 rlen 4 { align1 1Q };112 … sampler MsgDesc: gather4 SIMD16 Surface = 2 Sampler = 0 mlen 4 rlen 8 { align1 1H };122 … sampler MsgDesc: gather4 SIMD8 Surface = 2 Sampler = 0 mlen 4 rlen 4 { align1 1Q };124 … sampler MsgDesc: gather4 SIMD16 Surface = 2 Sampler = 0 mlen 7 rlen 8 { align1 1H };150 … sampler MsgDesc: gather4 SIMD8 Surface = 2 Sampler = 0 mlen 4 rlen 4 { align1 1Q };152 … sampler MsgDesc: gather4 SIMD16 Surface = 2 Sampler = 0 mlen 8 rlen 8 { align1 1H };164 … sampler MsgDesc: gather4 SIMD8 Surface = 2 Sampler = 0 mlen 3 rlen 4 { align1 1Q };[all …]
64 … sampler MsgDesc: gather4 SIMD8 Surface = 2 Sampler = 0 mlen 3 rlen 4 { align1 1Q };66 … sampler MsgDesc: gather4 SIMD16 Surface = 2 Sampler = 0 mlen 5 rlen 8 { align1 1H };104 … sampler MsgDesc: gather4 SIMD8 Surface = 2 Sampler = 0 mlen 4 rlen 4 { align1 1Q };106 … sampler MsgDesc: gather4 SIMD16 Surface = 2 Sampler = 0 mlen 7 rlen 8 { align1 1H };376 … sampler MsgDesc: gather4 SIMD8 Surface = 2 Sampler = 0 mlen 5 rlen 4 { align1 1Q };378 … sampler MsgDesc: gather4 SIMD16 Surface = 2 Sampler = 0 mlen 9 rlen 8 { align1 1H };384 … sampler MsgDesc: gather4 SIMD4x2 Surface = 1 Sampler = 0 mlen 2 rlen 1 { align16 1Q };448 … sampler MsgDesc: gather4 SIMD4x2 Surface = 3 Sampler = 0 mlen 2 rlen 1 { align16 1Q };450 … sampler MsgDesc: gather4 SIMD4x2 Surface = 4 Sampler = 1 mlen 2 rlen 1 { align16 1Q };452 … sampler MsgDesc: gather4 SIMD4x2 Surface = 5 Sampler = 2 mlen 2 rlen 1 { align16 1Q };[all …]
186 case gather4: return "GATHER4"; in opname()218 {gather4,"GATHER4"},233 return op == gather4 || op == gather4_c || in is_gather()869 src.opcode = src.opcode == gather4_o ? gather4 : gather4_c; in emit_tex_tg4()1040 (offset ? gather4_o : gather4); in get_opcode()
56 gather4 = FETCH_OP_GATHER4, enumerator
50 … sampler MsgDesc: gather4 SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };54 … sampler MsgDesc: gather4 SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 8 { align1 1H };88 … sampler MsgDesc: gather4 SIMD8 Surface = 0 Sampler = 0 mlen 3 rlen 4 { align1 1Q };104 … sampler MsgDesc: gather4 SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };106 … sampler MsgDesc: gather4 SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 8 { align1 1H };328 … sampler MsgDesc: gather4 SIMD8 Surface = 0 Sampler = 0 mlen 4 rlen 4 { align1 1Q };456 … sampler MsgDesc: gather4 SIMD8 Surface = 0 Sampler = 0 mlen 5 rlen 4 { align1 1Q };546 … sampler MsgDesc: gather4 SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };548 … sampler MsgDesc: gather4 SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 8 { align1 1H };692 … sampler MsgDesc: gather4 SIMD8 Surface = 2 Sampler = 2 mlen 3 rlen 4 { align1 1Q };[all …]
372 TexInstr expect(TexInstr::gather4, RegisterVec4(1001), {0,1,2,3}, RegisterVec4(2002), 27, 7); in TEST_F()380 TexInstr expect(TexInstr::gather4, RegisterVec4(1001), {0,1,2,3}, RegisterVec4(2002), 27, 7); in TEST_F()
472 TexInstr tex(TexInstr::gather4, in TEST_F()479 EXPECT_EQ(tex.opcode(), TexInstr::gather4); in TEST_F()
97 - cherry-ignore: add "radeonsi: workaround for gather4 on integer cube
136 - radeonsi: workaround for gather4 on integer cube maps
744 - ac/nir: Rewrite gather4 integer workaround based on radeonsi745 - ac/nir: Fix gather4 integer wa with unnormalized coordinates
72 … sampler MsgDesc: gather4 SIMD8 Surface = 0 Sampler = 0 mlen 3 rlen 4 { align1 1Q };100 … sampler MsgDesc: gather4 SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };102 … sampler MsgDesc: gather4 SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 8 { align1 1H };146 … sampler MsgDesc: gather4 SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };148 … sampler MsgDesc: gather4 SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 8 { align1 1H };320 … sampler MsgDesc: gather4 SIMD8 Surface = 0 Sampler = 0 mlen 4 rlen 4 { align1 1Q };520 … sampler MsgDesc: gather4 SIMD8 Surface = 0 Sampler = 0 mlen 5 rlen 4 { align1 1Q };684 … sampler MsgDesc: gather4 SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };686 … sampler MsgDesc: gather4 SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 8 { align1 1H };844 … sampler MsgDesc: gather4 SIMD8 Surface = 2 Sampler = 2 mlen 3 rlen 4 { align1 1Q };[all …]
1036 "llvm.amdgcn.image.gather4.2d",1037 "llvm.amdgcn.image.gather4.2darray",1038 "llvm.amdgcn.image.gather4.b.2d",1039 "llvm.amdgcn.image.gather4.b.2darray",1040 "llvm.amdgcn.image.gather4.b.cl.2d",1041 "llvm.amdgcn.image.gather4.b.cl.2darray",1042 "llvm.amdgcn.image.gather4.b.cl.cube",1043 "llvm.amdgcn.image.gather4.b.cl.o.2d",1044 "llvm.amdgcn.image.gather4.b.cl.o.2darray",1045 "llvm.amdgcn.image.gather4.b.cl.o.cube",[all …]
407 amdgcn_image_gather4, // llvm.amdgcn.image.gather4408 amdgcn_image_gather4_b, // llvm.amdgcn.image.gather4.b409 amdgcn_image_gather4_b_cl, // llvm.amdgcn.image.gather4.b.cl410 amdgcn_image_gather4_b_cl_o, // llvm.amdgcn.image.gather4.b.cl.o411 amdgcn_image_gather4_b_o, // llvm.amdgcn.image.gather4.b.o412 amdgcn_image_gather4_c, // llvm.amdgcn.image.gather4.c413 amdgcn_image_gather4_c_b, // llvm.amdgcn.image.gather4.c.b414 amdgcn_image_gather4_c_b_cl, // llvm.amdgcn.image.gather4.c.b.cl415 amdgcn_image_gather4_c_b_cl_o, // llvm.amdgcn.image.gather4.c.b.cl.o416 amdgcn_image_gather4_c_b_o, // llvm.amdgcn.image.gather4.c.b.o[all …]
400 amdgcn_image_gather4, // llvm.amdgcn.image.gather4401 amdgcn_image_gather4_b, // llvm.amdgcn.image.gather4.b402 amdgcn_image_gather4_b_cl, // llvm.amdgcn.image.gather4.b.cl403 amdgcn_image_gather4_b_cl_o, // llvm.amdgcn.image.gather4.b.cl.o404 amdgcn_image_gather4_b_o, // llvm.amdgcn.image.gather4.b.o405 amdgcn_image_gather4_c, // llvm.amdgcn.image.gather4.c406 amdgcn_image_gather4_c_b, // llvm.amdgcn.image.gather4.c.b407 amdgcn_image_gather4_c_b_cl, // llvm.amdgcn.image.gather4.c.b.cl408 amdgcn_image_gather4_c_b_cl_o, // llvm.amdgcn.image.gather4.c.b.cl.o409 amdgcn_image_gather4_c_b_o, // llvm.amdgcn.image.gather4.c.b.o[all …]
802 // gather4 intrinsics