| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | R600ClauseMergePass.cpp | 88 .getImm(); in getCFAluSize()
95 .getImm(); in isCFAluEnabled()
136 if (LatrCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
137 RootCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
138 (LatrCFAlu.getOperand(KBank0Idx).getImm() != in mergeIfPossible()
139 RootCFAlu.getOperand(KBank0Idx).getImm() || in mergeIfPossible()
140 LatrCFAlu.getOperand(KBank0LineIdx).getImm() != in mergeIfPossible()
141 RootCFAlu.getOperand(KBank0LineIdx).getImm())) { in mergeIfPossible()
152 if (LatrCFAlu.getOperand(Mode1Idx).getImm() && in mergeIfPossible()
153 RootCFAlu.getOperand(Mode1Idx).getImm() && in mergeIfPossible()
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| D | GCNDPPCombine.cpp | 199 assert(0LL == (Mod0->getImm() & ~(SISrcMods::ABS | SISrcMods::NEG))); in createDPPInst()
200 DPPInst.addImm(Mod0->getImm()); in createDPPInst()
222 assert(0LL == (Mod1->getImm() & ~(SISrcMods::ABS | SISrcMods::NEG))); in createDPPInst()
223 DPPInst.addImm(Mod1->getImm()); in createDPPInst()
282 if (OldOpnd->getImm() == 0) in isIdentityValue()
289 if (static_cast<uint32_t>(OldOpnd->getImm()) == in isIdentityValue()
295 if (static_cast<int32_t>(OldOpnd->getImm()) == in isIdentityValue()
301 if (static_cast<int32_t>(OldOpnd->getImm()) == in isIdentityValue()
309 if (OldOpnd->getImm() == 1) in isIdentityValue()
350 return (Imm->getImm() & Mask) == Value; in hasNoImmOrEqual()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMInstPrinter.cpp | 105 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm())); in printInst()
116 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0); in printInst()
127 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm())); in printInst()
136 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) { in printInst()
142 << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())) << markup(">"); in printInst()
165 MI->getOperand(3).getImm() == -4) { in printInst()
194 MI->getOperand(4).getImm() == 4) { in printInst()
289 switch (MI->getOperand(0).getImm()) { in printInst()
318 O << markup("<imm:") << '#' << formatImm(Op.getImm()) << markup(">"); in printOperand()
362 int32_t OffImm = (int32_t)MO1.getImm(); in printThumbLdrLabelOperand()
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| D | ARMMCCodeEmitter.cpp | 234 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm(); in getLdStmModeOpValue()
329 return MO.getImm(); in getModImmOpValue()
346 unsigned SoImm = MO.getImm(); in getT2SOImmOpValue()
377 return 64 - MI.getOperand(Op).getImm(); in getNEONVcvtImm32OpValue()
422 return (invert ? (MO.getImm() ^ 0xff) : MO.getImm()) >> shift; in getExpandedImmOpValue()
586 return static_cast<unsigned>(MO.getImm()); in getMachineOpValue()
605 int32_t SImm = MO1.getImm(); in EncodeAddrModeOpValues()
633 if (MO.isImm()) return MO.getImm(); in getBranchTargetOpValue()
671 return encodeThumbBLOffset(MO.getImm()); in getThumbBLTargetOpValue()
684 return encodeThumbBLOffset(MO.getImm()); in getThumbBLXTargetOpValue()
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| D | ARMMCTargetDesc.cpp | 40 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) && in getMCRDeprecationInfo()
41 (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) && in getMCRDeprecationInfo()
44 (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) { in getMCRDeprecationInfo()
45 if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) { in getMCRDeprecationInfo()
46 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) { in getMCRDeprecationInfo()
53 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) { in getMCRDeprecationInfo()
60 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 && in getMCRDeprecationInfo()
61 (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) { in getMCRDeprecationInfo()
72 MI.getOperand(1).getImm() != 8) { in getITDeprecationInfo()
254 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL) in isUnconditionalBranch()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZAsmPrinter.cpp | 37 .addImm(MI->getOperand(1).getImm()); in lowerRILow()
42 .addImm(MI->getOperand(2).getImm()); in lowerRILow()
51 .addImm(MI->getOperand(1).getImm()); in lowerRIHigh()
56 .addImm(MI->getOperand(2).getImm()); in lowerRIHigh()
66 .addImm(MI->getOperand(3).getImm()) in lowerRIEfLow()
67 .addImm(MI->getOperand(4).getImm()) in lowerRIEfLow()
68 .addImm(MI->getOperand(5).getImm()); in lowerRIEfLow()
112 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorLoad()
122 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorStore()
137 .addImm(MI->getOperand(0).getImm()) in EmitInstruction()
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| D | SystemZInstrInfo.cpp | 98 LowOffsetOp.setImm(LowOffsetOp.getImm() + 8); in splitMove()
107 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm()); in splitMove()
108 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm()); in splitMove()
124 OffsetMO.getImm()); in splitAdjDynAlloc()
144 MI.getOperand(1).setImm(uint32_t(MI.getOperand(1).getImm())); in expandRIPseudo()
180 MI.getOperand(2).getImm()); in expandRXYPseudo()
293 unsigned CCValid = WorkingMI.getOperand(3).getImm(); in commuteInstructionImpl()
294 unsigned CCMask = WorkingMI.getOperand(4).getImm(); in commuteInstructionImpl()
313 MI.getOperand(2).getImm() == 0 && MI.getOperand(3).getReg() == 0) { in isSimpleMove()
336 MI.getOperand(1).getImm() != 0 || !MI.getOperand(3).isFI() || in isStackSlotCopy()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| D | AMDGPUInstPrinter.cpp | 40 O << formatHex(MI->getOperand(OpNo).getImm() & 0xf); in printU4ImmOperand()
45 O << formatHex(MI->getOperand(OpNo).getImm() & 0xff); in printU8ImmOperand()
53 int64_t Imm = MI->getOperand(OpNo).getImm(); in printU16ImmOperand()
62 O << formatDec(MI->getOperand(OpNo).getImm() & 0xf); in printU4ImmDecOperand()
67 O << formatDec(MI->getOperand(OpNo).getImm() & 0xff); in printU8ImmDecOperand()
72 O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff); in printU16ImmDecOperand()
78 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff); in printU32ImmOperand()
83 if (MI->getOperand(OpNo).getImm()) { in printNamedBit()
105 if (MI->getOperand(OpNo).getImm()) { in printMBUFOffset()
114 uint16_t Imm = MI->getOperand(OpNo).getImm(); in printOffset()
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| D | R600MCCodeEmitter.cpp | 114 uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset in encodeInstruction()
123 int64_t Sampler = MI.getOperand(14).getImm(); in encodeInstruction()
126 MI.getOperand(2).getImm(), in encodeInstruction()
127 MI.getOperand(3).getImm(), in encodeInstruction()
128 MI.getOperand(4).getImm(), in encodeInstruction()
129 MI.getOperand(5).getImm() in encodeInstruction()
132 MI.getOperand(6).getImm() & 0x1F, in encodeInstruction()
133 MI.getOperand(7).getImm() & 0x1F, in encodeInstruction()
134 MI.getOperand(8).getImm() & 0x1F in encodeInstruction()
194 return MO.getImm(); in getMachineOpValue()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/MCTargetDesc/ |
| D | LanaiMCCodeEmitter.cpp | 115 return static_cast<unsigned>(MCOp.getImm()); in getMachineOpValue()
138 unsigned AluCode = AluOp.getImm(); in adjustPqBits()
145 ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
153 if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
196 assert((LPAC::getAluOp(AluOp.getImm()) == LPAC::ADD) && in getRiMemoryOpValue()
201 assert(isInt<16>(Op2.getImm()) && in getRiMemoryOpValue()
204 Encoding |= (Op2.getImm() & 0xffff); in getRiMemoryOpValue()
205 if (Op2.getImm() != 0) { in getRiMemoryOpValue()
206 if (LPAC::isPreOp(AluOp.getImm())) in getRiMemoryOpValue()
208 if (LPAC::isPostOp(AluOp.getImm())) in getRiMemoryOpValue()
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| D | LanaiInstPrinter.cpp | 49 unsigned AluCode = MI->getOperand(3).getImm(); in usesGivenOffset()
51 (MI->getOperand(2).getImm() == AddOffset || in usesGivenOffset()
52 MI->getOperand(2).getImm() == -AddOffset); in usesGivenOffset()
56 unsigned AluCode = MI->getOperand(3).getImm(); in isPreIncrementForm()
61 unsigned AluCode = MI->getOperand(3).getImm(); in isPostIncrementForm()
66 if (MI->getOperand(2).getImm() < 0) in decIncOperator()
156 OS << formatHex(Op.getImm()); in printOperand()
167 OS << '[' << formatHex(Op.getImm()) << ']'; in printMemImmOperand()
181 OS << formatHex(Op.getImm() << 16); in printHi16ImmOperand()
193 OS << formatHex((Op.getImm() << 16) | 0xffff); in printHi16AndImmOperand()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCInstPrinter.cpp | 97 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
98 unsigned char MB = MI->getOperand(3).getImm(); in printInst()
99 unsigned char ME = MI->getOperand(4).getImm(); in printInst()
131 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
132 unsigned char ME = MI->getOperand(3).getImm(); in printInst()
154 unsigned char TH = MI->getOperand(0).getImm(); in printInst()
178 unsigned char L = MI->getOperand(0).getImm(); in printInst()
204 unsigned Code = MI->getOperand(OpNo).getImm(); in printPredicateOperand()
300 unsigned Code = MI->getOperand(OpNo).getImm(); in printATBitsAsHint()
309 unsigned int Value = MI->getOperand(OpNo).getImm(); in printU1ImmOperand()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64MCCodeEmitter.cpp | 208 return static_cast<unsigned>(MO.getImm()); in getMachineOpValue()
219 ImmVal = static_cast<uint32_t>(MO.getImm()); in getLdStUImm12OpValue()
240 return MO.getImm(); in getAdrLabelOpValue()
265 assert(AArch64_AM::getShiftType(MO1.getImm()) == AArch64_AM::LSL && in getAddSubImmOpValue()
267 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm()); in getAddSubImmOpValue()
271 return MO.getImm() | (ShiftVal == 0 ? 0 : (1 << ShiftVal)); in getAddSubImmOpValue()
302 return MO.getImm(); in getCondBranchTargetOpValue()
324 return MO.getImm(); in getLoadLiteralOpValue()
340 unsigned SignExtend = MI.getOperand(OpIdx).getImm(); in getMemExtendOpValue()
341 unsigned DoShift = MI.getOperand(OpIdx + 1).getImm(); in getMemExtendOpValue()
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| D | AArch64InstPrinter.cpp | 82 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) { in printInst()
85 switch (Op3.getImm()) { in printInst()
121 int64_t immr = Op2.getImm(); in printInst()
122 int64_t imms = Op3.getImm(); in printInst()
152 if (Op2.getImm() > Op3.getImm()) { in printInst()
155 << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1; in printInst()
163 << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1; in printInst()
171 int ImmR = MI->getOperand(3).getImm(); in printInst()
172 int ImmS = MI->getOperand(4).getImm(); in printInst()
239 int Shift = MI->getOperand(2).getImm(); in printInst()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/AsmParser/ |
| D | PPCAsmParser.cpp | 249 int64_t getImm() const { in getImm() function
310 bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); } in isU1Imm()
311 bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); } in isU2Imm()
312 bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); } in isU3Imm()
313 bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); } in isU4Imm()
314 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); } in isU5Imm()
315 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); } in isS5Imm()
316 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); } in isU6Imm()
318 isUInt<6>(getImm()) && in isU6ImmX2()
319 (getImm() & 1) == 0; } in isU6ImmX2()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/AsmParser/ |
| D | LanaiAsmParser.cpp | 159 const MCExpr *getImm() const { in getImm() function
407 addExpr(Inst, getImm()); in addImmOperands()
412 addExpr(Inst, getImm()); in addBrTargetOperands()
417 addExpr(Inst, getImm()); in addCallTargetOperands()
422 addExpr(Inst, getImm()); in addCondCodeOperands()
456 addExpr(Inst, getImm()); in addImmShiftOperands()
461 addExpr(Inst, getImm()); in addImm10Operands()
466 if (const MCConstantExpr *ConstExpr = dyn_cast<MCConstantExpr>(getImm())) in addLoImm16Operands()
469 else if (isa<LanaiMCExpr>(getImm())) { in addLoImm16Operands()
471 const LanaiMCExpr *SymbolRefExpr = dyn_cast<LanaiMCExpr>(getImm()); in addLoImm16Operands()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/MCTargetDesc/ |
| D | WebAssemblyMCCodeEmitter.cpp | 96 encodeSLEB128(int32_t(MO.getImm()), OS); in encodeInstruction()
99 encodeULEB128(uint32_t(MO.getImm()), OS); in encodeInstruction()
102 encodeSLEB128(int64_t(MO.getImm()), OS); in encodeInstruction()
105 OS << uint8_t(MO.getImm()); in encodeInstruction()
108 support::endian::write<uint8_t>(OS, MO.getImm(), support::little); in encodeInstruction()
111 support::endian::write<uint16_t>(OS, MO.getImm(), support::little); in encodeInstruction()
114 support::endian::write<uint32_t>(OS, MO.getImm(), support::little); in encodeInstruction()
117 support::endian::write<uint64_t>(OS, MO.getImm(), support::little); in encodeInstruction()
122 encodeULEB128(uint64_t(MO.getImm()), OS); in encodeInstruction()
125 encodeULEB128(uint64_t(MO.getImm()), OS); in encodeInstruction()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64AsmPrinter.cpp | 314 uint32_t AccessInfo = MI.getOperand(1).getImm(); in LowerHWASAN_CHECK_MEMACCESS()
583 O << MO.getImm(); in printOperand()
651 if (MO.isImm() && MO.getImm() == 0) { in PrintAsmOperand()
905 int64_t CallTarget = Opers.getCallTarget().getImm(); in LowerPATCHPOINT()
1011 int64_t Imm = MI->getOperand(0).getImm(); in EmitInstruction()
1055 MI->getOperand(1).getImm() == 0) { in EmitInstruction()
1059 TmpInst.addOperand(MCOperand::createImm(MI->getOperand(1).getImm())); in EmitInstruction()
1219 TS->EmitARM64WinCFIAllocStack(MI->getOperand(0).getImm()); in EmitInstruction()
1223 TS->EmitARM64WinCFISaveFPLR(MI->getOperand(0).getImm()); in EmitInstruction()
1227 assert(MI->getOperand(0).getImm() < 0 && in EmitInstruction()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| D | SystemZInstPrinter.cpp | 51 O << MO.getImm(); in printOperand()
71 int64_t Value = MI->getOperand(OpNum).getImm(); in printUImmOperand()
78 int64_t Value = MI->getOperand(OpNum).getImm(); in printSImmOperand()
153 O.write_hex(MO.getImm()); in printPCRelOperand()
189 MI->getOperand(OpNum + 1).getImm(), 0, O); in printBDAddrOperand()
195 MI->getOperand(OpNum + 1).getImm(), in printBDXAddrOperand()
202 uint64_t Disp = MI->getOperand(OpNum + 1).getImm(); in printBDLAddrOperand()
203 uint64_t Length = MI->getOperand(OpNum + 2).getImm(); in printBDLAddrOperand()
213 uint64_t Disp = MI->getOperand(OpNum + 1).getImm(); in printBDRAddrOperand()
224 MI->getOperand(OpNum + 1).getImm(), in printBDVAddrOperand()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | StackMaps.h | 47 uint64_t getID() const { return MI->getOperand(IDPos).getImm(); } in getID()
51 return MI->getOperand(NBytesPos).getImm(); in getNumPatchBytes()
101 uint64_t getID() const { return getMetaOper(IDPos).getImm(); } in getID()
105 return getMetaOper(NBytesPos).getImm(); in getNumPatchBytes()
115 return getMetaOper(CCPos).getImm(); in getCallingConv()
122 return MI->getOperand(getMetaIdx(NArgPos)).getImm(); in getNumCallArgs()
173 return MI->getOperand(NCallArgsPos).getImm() + MetaEnd; in getVarIdx()
177 uint64_t getID() const { return MI->getOperand(IDPos).getImm(); } in getID()
181 return MI->getOperand(NBytesPos).getImm(); in getNumPatchBytes()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiMemAluCombiner.cpp | 178 return Op1.getImm() == Op2.getImm(); in isSameOperand()
186 (Op.isImm() && Op.getImm() == 0)); in isZeroOperand()
267 InstrBuilder.addImm(AluOffset.getImm()); in insertMergedInstruction()
311 ((Offset.getImm() == 0 && in isSuitableAluInstr()
314 ((IsSpls && isInt<10>(Op2.getImm())) || in isSuitableAluInstr()
315 (!IsSpls && isInt<16>(Op2.getImm())))) || in isSuitableAluInstr()
316 Offset.getImm() == Op2.getImm())) in isSuitableAluInstr()
376 LPAC::AluCode AluOpcode = static_cast<LPAC::AluCode>(AluOperand.getImm()); in combineMemAluInBasicBlock()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCMIPeephole.cpp | 167 return MI->getOperand(3).getImm(); in getKnownLeadingZeroCount()
170 MI->getOperand(3).getImm() <= 63 - MI->getOperand(2).getImm()) in getKnownLeadingZeroCount()
171 return MI->getOperand(3).getImm(); in getKnownLeadingZeroCount()
176 MI->getOperand(3).getImm() <= MI->getOperand(4).getImm()) in getKnownLeadingZeroCount()
177 return 32 + MI->getOperand(3).getImm(); in getKnownLeadingZeroCount()
180 uint16_t Imm = MI->getOperand(2).getImm(); in getKnownLeadingZeroCount()
334 int Immed = MI.getOperand(3).getImm(); in simplifyCode()
393 unsigned DefImmed = DefMI->getOperand(3).getImm(); in simplifyCode()
442 (DefMI->getOperand(2).getImm() == 0 || in simplifyCode()
443 DefMI->getOperand(2).getImm() == 3)) { in simplifyCode()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonCopyToCombine.cpp | 157 bool NotExt = Op1.isImm() && isInt<8>(Op1.getImm()); in isCombinableInstType()
176 return !Op.isImm() || !isInt<N>(Op.getImm()); in isGreaterThanNBitTFRI()
657 int64_t V = HiOperand.getImm(); in emitConst64()
658 V = (V << 32) | (0x0ffffffffLL & LoOperand.getImm()); in emitConst64()
675 .addImm(LoOperand.getImm()); in emitCombineII()
680 .addImm(HiOperand.getImm()) in emitCombineII()
691 .addImm(LoOperand.getImm()); in emitCombineII()
696 .addImm(HiOperand.getImm()) in emitCombineII()
706 .addImm(LoOperand.getImm()); in emitCombineII()
711 .addImm(HiOperand.getImm()) in emitCombineII()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/AsmParser/ |
| D | RISCVAsmParser.cpp | 308 bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); in isBareSimmNLsb0()
311 IsValid = RISCVAsmParser::classifySymbolRef(getImm(), VK, Imm); in isBareSimmNLsb0()
323 if (!isImm() || evaluateConstantImm(getImm(), Imm, VK)) in isBareSymbol()
325 return RISCVAsmParser::classifySymbolRef(getImm(), VK, Imm) && in isBareSymbol()
333 if (!isImm() || evaluateConstantImm(getImm(), Imm, VK)) in isCallSymbol()
335 return RISCVAsmParser::classifySymbolRef(getImm(), VK, Imm) && in isCallSymbol()
344 if (!isImm() || evaluateConstantImm(getImm(), Imm, VK)) in isTPRelAddSymbol()
346 return RISCVAsmParser::classifySymbolRef(getImm(), VK, Imm) && in isTPRelAddSymbol()
357 const MCExpr *Val = getImm(); in isFenceArg()
381 const MCExpr *Val = getImm(); in isFRMArg()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/VE/InstPrinter/ |
| D | VEInstPrinter.cpp | 63 assert(isInt<32>(MO.getImm()) && "Immediate too large"); in printOperand()
64 int32_t TruncatedImm = static_cast<int32_t>(MO.getImm()); in printOperand()
86 if (!MO.isImm() || MO.getImm() != 0) { in printMemASXOperand()
106 if (!MO.isImm() || MO.getImm() != 0) { in printMemASOperand()
116 int CC = (int)MI->getOperand(opNum).getImm(); in printCCOperand()
|