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/third_party/mesa3d/src/panfrost/midgard/
Dmidgard_emit.c78 mir_pack_mod(midgard_instruction *ins, unsigned i, bool scalar) in mir_pack_mod() argument
80 bool integer = midgard_is_integer_op(ins->op); in mir_pack_mod()
81 unsigned base_size = max_bitsize_for_alu(ins); in mir_pack_mod()
82 unsigned sz = nir_alu_type_get_type_size(ins->src_types[i]); in mir_pack_mod()
86 mir_get_imod(ins->src_shift[i], ins->src_types[i], half, scalar) : in mir_pack_mod()
87 ((ins->src_abs[i] << 0) | in mir_pack_mod()
88 ((ins->src_neg[i] << 1))); in mir_pack_mod()
123 vector_to_scalar_alu(midgard_vector_alu v, midgard_instruction *ins) in vector_to_scalar_alu() argument
125 bool is_full = nir_alu_type_get_type_size(ins->dest_type) == 32; in vector_to_scalar_alu()
127 bool half_0 = nir_alu_type_get_type_size(ins->src_types[0]) == 16; in vector_to_scalar_alu()
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Dmir.c28 void mir_rewrite_index_src_single(midgard_instruction *ins, unsigned old, unsigned new) in mir_rewrite_index_src_single() argument
30 mir_foreach_src(ins, i) { in mir_rewrite_index_src_single()
31 if (ins->src[i] == old) in mir_rewrite_index_src_single()
32 ins->src[i] = new; in mir_rewrite_index_src_single()
36 void mir_rewrite_index_dst_single(midgard_instruction *ins, unsigned old, unsigned new) in mir_rewrite_index_dst_single() argument
38 if (ins->dest == old) in mir_rewrite_index_dst_single()
39 ins->dest = new; in mir_rewrite_index_dst_single()
43 mir_rewrite_index_src_single_swizzle(midgard_instruction *ins, unsigned old, unsigned new, unsigned… in mir_rewrite_index_src_single_swizzle() argument
45 for (unsigned i = 0; i < ARRAY_SIZE(ins->src); ++i) { in mir_rewrite_index_src_single_swizzle()
46 if (ins->src[i] != old) continue; in mir_rewrite_index_src_single_swizzle()
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Dmidgard_print.c118 mir_print_embedded_constant(midgard_instruction *ins, unsigned src_idx) in mir_print_embedded_constant() argument
122 unsigned base_size = max_bitsize_for_alu(ins); in mir_print_embedded_constant()
123 unsigned sz = nir_alu_type_get_type_size(ins->src_types[src_idx]); in mir_print_embedded_constant()
125 unsigned mod = mir_pack_mod(ins, src_idx, false); in mir_print_embedded_constant()
126 unsigned *swizzle = ins->swizzle[src_idx]; in mir_print_embedded_constant()
127 midgard_reg_mode reg_mode = reg_mode_for_bitsize(max_bitsize_for_alu(ins)); in mir_print_embedded_constant()
128 unsigned comp_mask = effective_writemask(ins->op, ins->mask); in mir_print_embedded_constant()
130 unsigned max_comp = mir_components_for_type(ins->dest_type); in mir_print_embedded_constant()
147 mir_print_constant_component(stdout, &ins->constants, in mir_print_embedded_constant()
149 half, mod, ins->op); in mir_print_embedded_constant()
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Dmidgard_ra.c188 mir_foreach_instr_global(ctx, ins) { in mir_lower_special_reads()
189 switch (ins->type) { in mir_lower_special_reads()
191 mark_node_class(aluw, ins->dest); in mir_lower_special_reads()
192 mark_node_class(alur, ins->src[0]); in mir_lower_special_reads()
193 mark_node_class(alur, ins->src[1]); in mir_lower_special_reads()
194 mark_node_class(alur, ins->src[2]); in mir_lower_special_reads()
196 if (ins->compact_branch && ins->writeout) in mir_lower_special_reads()
197 mark_node_class(brar, ins->src[0]); in mir_lower_special_reads()
202 mark_node_class(aluw, ins->dest); in mir_lower_special_reads()
203 mark_node_class(ldst, ins->src[0]); in mir_lower_special_reads()
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Dmidgard_opt_dce.c34 can_cull_mask(compiler_context *ctx, midgard_instruction *ins) in can_cull_mask() argument
36 if (ins->dest >= ctx->temp_count) in can_cull_mask()
39 if (ins->dest == ctx->blend_src1) in can_cull_mask()
42 if (ins->type == TAG_LOAD_STORE_4) in can_cull_mask()
43 if (load_store_opcode_props[ins->op].props & LDST_SPECIAL_MASK) in can_cull_mask()
50 can_dce(midgard_instruction *ins) in can_dce() argument
52 if (ins->mask) in can_dce()
55 if (ins->compact_branch) in can_dce()
58 if (ins->type == TAG_LOAD_STORE_4) in can_dce()
59 if (load_store_opcode_props[ins->op].props & LDST_SIDE_FX) in can_dce()
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Dmidgard_compile.c189 midgard_instruction ins = { in v_branch() local
201 return ins; in v_branch()
205 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name) in attach_constants() argument
207 ins->has_constants = true; in attach_constants()
208 memcpy(&ins->constants, constants, 16); in attach_constants()
515 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), to); in emit_explicit_constant() local
516 attach_constants(ctx, &ins, constant_value, node + 1); in emit_explicit_constant()
517 emit_mir_instruction(ctx, ins); in emit_explicit_constant()
545 midgard_instruction ins = emit_image_op(ctx, instr, true); \
546 emit_atomic(ctx, instr, false, midgard_op_atomic_##op, ins.dest); \
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Dmir_promote_uniforms.c40 mir_is_ubo(midgard_instruction *ins) in mir_is_ubo() argument
42 return (ins->type == TAG_LOAD_STORE_4) && in mir_is_ubo()
43 (OP_IS_UBO_READ(ins->op)); in mir_is_ubo()
47 mir_is_direct_aligned_ubo(midgard_instruction *ins) in mir_is_direct_aligned_ubo() argument
49 return mir_is_ubo(ins) && in mir_is_direct_aligned_ubo()
50 !(ins->constants.u32[0] & 0xF) && in mir_is_direct_aligned_ubo()
51 (ins->src[1] == ~0) && in mir_is_direct_aligned_ubo()
52 (ins->src[2] == ~0); in mir_is_direct_aligned_ubo()
79 mir_foreach_instr_global(ctx, ins) { in mir_analyze_ranges()
80 if (!mir_is_direct_aligned_ubo(ins)) continue; in mir_analyze_ranges()
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Dmidgard_helper_invocations.c69 mir_foreach_instr_in_block(block, ins) { in mir_block_uses_helpers()
70 if (ins->type != TAG_TEXTURE_4) continue; in mir_block_uses_helpers()
71 if (mir_op_computes_derivatives(stage, ins->op)) in mir_block_uses_helpers()
152 mir_foreach_instr_in_block_rev(block, ins) { in mir_analyze_helper_terminate()
153 if (ins->type != TAG_TEXTURE_4) continue; in mir_analyze_helper_terminate()
154 if (!mir_op_computes_derivatives(ctx->stage, ins->op)) continue; in mir_analyze_helper_terminate()
156 ins->helper_terminate = true; in mir_analyze_helper_terminate()
168 mir_foreach_instr_in_block_rev(block, ins) { in mir_helper_block_update()
170 if (ins->dest >= temp_count || !BITSET_TEST(deps, ins->dest)) in mir_helper_block_update()
174 mir_foreach_src(ins, s) { in mir_helper_block_update()
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Dmidgard_opt_perspective.c55 mir_foreach_instr_in_block_safe(block, ins) { in midgard_opt_combine_projection()
57 if (ins->type != TAG_ALU_4) continue; in midgard_opt_combine_projection()
58 if (ins->op != midgard_alu_op_fmul) continue; in midgard_opt_combine_projection()
64 if (!mir_is_simple_swizzle(ins->swizzle[0], ins->mask)) continue; in midgard_opt_combine_projection()
65 if (!is_swizzle_0(ins->swizzle[1])) continue; in midgard_opt_combine_projection()
68 unsigned frcp = ins->src[1]; in midgard_opt_combine_projection()
69 unsigned to = ins->dest; in midgard_opt_combine_projection()
91 if (frcp_from != ins->src[0]) continue; in midgard_opt_combine_projection()
118 .mask = ins->mask, in midgard_opt_combine_projection()
132 mir_insert_instruction_before(ctx, ins, accel); in midgard_opt_combine_projection()
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Dcompiler.h322 mir_upload_ins(struct compiler_context *ctx, struct midgard_instruction ins) in mir_upload_ins() argument
325 memcpy(heap, &ins, sizeof(ins)); in mir_upload_ins()
330 emit_mir_instruction(struct compiler_context *ctx, struct midgard_instruction ins) in emit_mir_instruction() argument
332 midgard_instruction *u = mir_upload_ins(ctx, ins); in emit_mir_instruction()
340 struct midgard_instruction ins) in mir_insert_instruction_before() argument
342 struct midgard_instruction *u = mir_upload_ins(ctx, ins); in mir_insert_instruction_before()
348 mir_remove_instruction(struct midgard_instruction *ins) in mir_remove_instruction() argument
350 list_del(&ins->link); in mir_remove_instruction()
354 mir_prev_op(struct midgard_instruction *ins) in mir_prev_op() argument
356 return list_last_entry(&(ins->link), midgard_instruction, link); in mir_prev_op()
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Dmidgard_address.c228 mir_set_offset(compiler_context *ctx, midgard_instruction *ins, nir_src *offset, unsigned seg) in mir_set_offset() argument
231 ins->swizzle[1][i] = 0; in mir_set_offset()
232 ins->swizzle[2][i] = 0; in mir_set_offset()
240 ins->load_store.bitsize_toggle = true; in mir_set_offset()
241 ins->load_store.arg_comp = seg & 0x3; in mir_set_offset()
242 ins->load_store.arg_reg = (seg >> 2) & 0x7; in mir_set_offset()
243 ins->src[2] = nir_src_index(ctx, offset); in mir_set_offset()
244 ins->src_types[2] = nir_type_uint | nir_src_bit_size(*offset); in mir_set_offset()
247 ins->load_store.index_format = midgard_index_address_s32; in mir_set_offset()
249 ins->load_store.index_format = midgard_index_address_u64; in mir_set_offset()
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/third_party/mesa3d/src/panfrost/bifrost/
Dbi_opt_dce.c45 bi_foreach_instr_in_block_safe_rev(block, ins) { in bi_opt_dead_code_eliminate()
48 bi_foreach_dest(ins, d) { in bi_opt_dead_code_eliminate()
49 unsigned index = bi_get_node(ins->dest[d]); in bi_opt_dead_code_eliminate()
52 if (ins->op == BI_OPCODE_AXCHG_I32 || in bi_opt_dead_code_eliminate()
53 ins->op == BI_OPCODE_ACMPXCHG_I32 || in bi_opt_dead_code_eliminate()
54 ins->op == BI_OPCODE_ATOM_RETURN_I32 || in bi_opt_dead_code_eliminate()
55 ins->op == BI_OPCODE_ATOM1_RETURN_I32 || in bi_opt_dead_code_eliminate()
56 ins->op == BI_OPCODE_BLEND || in bi_opt_dead_code_eliminate()
57 ins->op == BI_OPCODE_ATEST || in bi_opt_dead_code_eliminate()
58 ins->op == BI_OPCODE_ZS_EMIT) in bi_opt_dead_code_eliminate()
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Dbi_lower_swizzle.c34 bi_lower_swizzle_16(bi_context *ctx, bi_instr *ins, unsigned src) in bi_lower_swizzle_16() argument
37 if (ins->src[src].swizzle == BI_SWIZZLE_H01) in bi_lower_swizzle_16()
41 switch (ins->op) { in bi_lower_swizzle_16()
72 if (src == 0 && ins->src[src].swizzle != BI_SWIZZLE_H10) in bi_lower_swizzle_16()
89 if (ins->src[src].swizzle == BI_SWIZZLE_H10) in bi_lower_swizzle_16()
98 bi_builder b = bi_init_builder(ctx, bi_after_instr(ins)); in bi_lower_swizzle_16()
99 bi_index dest = ins->dest[0]; in bi_lower_swizzle_16()
102 ins->dest[0] = tmp; in bi_lower_swizzle_16()
103 bi_swz_v2i16_to(&b, dest, bi_replace_index(ins->src[0], tmp)); in bi_lower_swizzle_16()
116 if (ins->src[src].type == BI_INDEX_CONSTANT) { in bi_lower_swizzle_16()
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Dbir.c30 bi_has_arg(const bi_instr *ins, bi_index arg) in bi_has_arg() argument
32 if (!ins) in bi_has_arg()
35 bi_foreach_src(ins, s) { in bi_has_arg()
36 if (bi_is_equiv(ins->src[s], arg)) in bi_has_arg()
66 bi_count_staging_registers(const bi_instr *ins) in bi_count_staging_registers() argument
68 enum bi_sr_count count = bi_opcode_props[ins->op].sr_count; in bi_count_staging_registers()
69 unsigned vecsize = ins->vecsize + 1; /* XXX: off-by-one */ in bi_count_staging_registers()
75 return bi_is_regfmt_16(ins->register_format) ? in bi_count_staging_registers()
80 return ins->sr_count; in bi_count_staging_registers()
87 bi_count_read_registers(const bi_instr *ins, unsigned s) in bi_count_read_registers() argument
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Dbi_opt_copy_prop.c31 bi_is_copy(bi_instr *ins) in bi_is_copy() argument
33 return (ins->op == BI_OPCODE_MOV_I32) && bi_is_ssa(ins->dest[0]) in bi_is_copy()
34 && (bi_is_ssa(ins->src[0]) || ins->src[0].type == BI_INDEX_FAU in bi_is_copy()
35 || ins->src[0].type == BI_INDEX_CONSTANT); in bi_is_copy()
39 bi_reads_fau(bi_instr *ins) in bi_reads_fau() argument
41 bi_foreach_src(ins, s) { in bi_reads_fau()
42 if (ins->src[s].type == BI_INDEX_FAU) in bi_reads_fau()
91 bi_foreach_instr_global_safe(ctx, ins) { in bi_opt_copy_prop()
92 if (bi_is_copy(ins)) { in bi_opt_copy_prop()
93 bi_index replace = ins->src[0]; in bi_opt_copy_prop()
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Dbifrost_isa.py125 def parse_instruction(ins, include_pseudo): argument
132 'staging': ins.attrib.get('staging', '').split('=')[0],
133 'staging_count': ins.attrib.get('staging', '=0').split('=')[1],
134 'dests': int(ins.attrib.get('dests', '1')),
135 'unused': ins.attrib.get('unused', False),
136 'pseudo': ins.attrib.get('pseudo', False),
137 'message': ins.attrib.get('message', 'none'),
138 'last': ins.attrib.get('last', False),
139 'table': ins.attrib.get('table', False),
142 if 'exact' in ins.attrib:
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrConv.td15 defm I32_WRAP_I64 : I<(outs I32:$dst), (ins I64:$src), (outs), (ins),
19 defm I64_EXTEND_S_I32 : I<(outs I64:$dst), (ins I32:$src), (outs), (ins),
23 defm I64_EXTEND_U_I32 : I<(outs I64:$dst), (ins I32:$src), (outs), (ins),
29 defm I32_EXTEND8_S_I32 : I<(outs I32:$dst), (ins I32:$src), (outs), (ins),
33 defm I32_EXTEND16_S_I32 : I<(outs I32:$dst), (ins I32:$src), (outs), (ins),
37 defm I64_EXTEND8_S_I64 : I<(outs I64:$dst), (ins I64:$src), (outs), (ins),
41 defm I64_EXTEND16_S_I64 : I<(outs I64:$dst), (ins I64:$src), (outs), (ins),
45 defm I64_EXTEND32_S_I64 : I<(outs I64:$dst), (ins I64:$src), (outs), (ins),
58 defm I32_TRUNC_S_SAT_F32 : I<(outs I32:$dst), (ins F32:$src), (outs), (ins),
63 defm I32_TRUNC_U_SAT_F32 : I<(outs I32:$dst), (ins F32:$src), (outs), (ins),
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/
DMSP430InstrFormats.td32 class MSP430Inst<dag outs, dag ins, int size, string asmstr> : Instruction {
39 dag InOperandList = ins;
47 dag outs, dag ins, string asmstr, list<dag> pattern>
48 : MSP430Inst<outs, ins, size, asmstr> {
64 dag outs, dag ins, string asmstr, list<dag> pattern>
65 : IForm<opcode, dest, 1, src, size, outs, ins, asmstr, pattern>;
68 dag outs, dag ins, string asmstr, list<dag> pattern>
69 : IForm8<opcode, DstReg, SrcReg, 2, outs, ins, asmstr, pattern> {
74 dag outs, dag ins, string asmstr, list<dag> pattern>
75 : IForm8<opcode, DstReg, SrcImm, 4, outs, ins, asmstr, pattern> {
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCInstrSPE.td140 def BRINC : EVXForm_1<527, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
144 def EFDABS : EFXForm_2<740, (outs sperc:$RT), (ins sperc:$RA),
148 def EFDADD : EFXForm_1<736, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
152 def EFDCFS : EFXForm_2a<751, (outs sperc:$RT), (ins spe4rc:$RB),
156 def EFDCFSF : EFXForm_2a<755, (outs sperc:$RT), (ins spe4rc:$RB),
159 def EFDCFSI : EFXForm_2a<753, (outs sperc:$RT), (ins gprc:$RB),
163 def EFDCFSID : EFXForm_2a<739, (outs sperc:$RT), (ins gprc:$RB),
167 def EFDCFUF : EFXForm_2a<754, (outs sperc:$RT), (ins spe4rc:$RB),
170 def EFDCFUI : EFXForm_2a<752, (outs sperc:$RT), (ins gprc:$RB),
174 def EFDCFUID : EFXForm_2a<738, (outs sperc:$RT), (ins gprc:$RB),
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrSystem.td17 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", []>, TB;
20 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
25 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
26 def UD2B : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
29 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
30 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
34 def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>, Requires<[Not64BitMode]>;
36 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3", [(int_x86_int (i8 3))]>;
45 def INT : Ii8<0xcd, RawFrm, (outs), (ins u8imm:$trap), "int\t$trap",
49 def SYSCALL : I<0x05, RawFrm, (outs), (ins), "syscall", []>, TB;
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DX86InstrFPStack.td128 def FP32_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP32:$src),
130 def FP32_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP32:$src),
132 def FP32_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP32:$src),
134 def FP64_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP64:$src),
136 def FP64_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP64:$src),
138 def FP64_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP64:$src),
140 def FP80_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP80:$src),
142 def FP80_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP80:$src),
144 def FP80_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP80:$src),
171 class FpIf32<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
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DX86InstrControl.td23 def RETL : I <0xC3, RawFrm, (outs), (ins variable_ops),
25 def RETQ : I <0xC3, RawFrm, (outs), (ins variable_ops),
27 def RETW : I <0xC3, RawFrm, (outs), (ins),
29 def RETIL : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
31 def RETIQ : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
33 def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt),
35 def LRETL : I <0xCB, RawFrm, (outs), (ins),
37 def LRETQ : RI <0xCB, RawFrm, (outs), (ins),
39 def LRETW : I <0xCB, RawFrm, (outs), (ins),
41 def LRETIL : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/
DXCoreInstrFormats.td12 class InstXCore<int sz, dag outs, dag ins, string asmstr, list<dag> pattern>
18 dag InOperandList = ins;
26 class PseudoInstXCore<dag outs, dag ins, string asmstr, list<dag> pattern>
27 : InstXCore<0, outs, ins, asmstr, pattern> {
35 class _F3R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
36 : InstXCore<2, outs, ins, asmstr, pattern> {
44 class _F3RImm<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
45 : _F3R<opc, outs, ins, asmstr, pattern> {
49 class _FL3R<bits<9> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
50 : InstXCore<4, outs, ins, asmstr, pattern> {
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/third_party/mesa3d/src/compiler/clc/
Dclc_helpers.cpp131 void parseEntryPoint(const spv_parsed_instruction_t *ins) in parseEntryPoint() argument
133 assert(ins->num_operands >= 3); in parseEntryPoint()
135 const spv_parsed_operand_t *op = &ins->operands[1]; in parseEntryPoint()
139 uint32_t funcId = ins->words[op->offset]; in parseEntryPoint()
146 op = &ins->operands[2]; in parseEntryPoint()
148 const char *name = reinterpret_cast<const char *>(ins->words + op->offset); in parseEntryPoint()
153 void parseFunction(const spv_parsed_instruction_t *ins) in parseFunction() argument
155 assert(ins->num_operands == 4); in parseFunction()
157 const spv_parsed_operand_t *op = &ins->operands[1]; in parseFunction()
161 uint32_t funcId = ins->words[op->offset]; in parseFunction()
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/third_party/mesa3d/src/asahi/compiler/
Dagx_register_allocate.c285 agx_foreach_instr_global(ctx, ins) { in agx_ra()
286 agx_foreach_src(ins, s) { in agx_ra()
287 if (ins->src[s].type == AGX_INDEX_NORMAL) { in agx_ra()
288 unsigned v = ssa_to_reg[ins->src[s].value]; in agx_ra()
289 ins->src[s] = agx_replace_index(ins->src[s], agx_register(v, ins->src[s].size)); in agx_ra()
293 agx_foreach_dest(ins, d) { in agx_ra()
294 if (ins->dest[d].type == AGX_INDEX_NORMAL) { in agx_ra()
295 unsigned v = ssa_to_reg[ins->dest[d].value]; in agx_ra()
296 ins->dest[d] = agx_replace_index(ins->dest[d], agx_register(v, ins->dest[d].size)); in agx_ra()
301 agx_foreach_instr_global_safe(ctx, ins) { in agx_ra()
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