Searched refs:is_mec (Results 1 – 3 of 3) sorted by relevance
| /third_party/mesa3d/src/amd/vulkan/ |
| D | si_cmd_buffer.c | 927 si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, bool is_mec, in si_cs_emit_write_event_eop() argument
935 unsigned is_gfx8_mec = is_mec && gfx_level < GFX9; in si_cs_emit_write_event_eop()
948 if (gfx_level == GFX9 && !is_mec) { in si_cs_emit_write_event_eop()
974 if (is_mec) { in si_cs_emit_write_event_eop()
1029 si_emit_acquire_mem(struct radeon_cmdbuf *cs, bool is_mec, bool is_gfx9, unsigned cp_coher_cntl) in si_emit_acquire_mem() argument
1031 if (is_mec || is_gfx9) { in si_emit_acquire_mem()
1033 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, false) | PKT3_SHADER_TYPE_S(is_mec)); in si_emit_acquire_mem()
1052 uint32_t *flush_cnt, uint64_t flush_va, bool is_mec, in gfx10_cs_emit_cache_flush() argument
1214 !is_mec) { in gfx10_cs_emit_cache_flush()
1233 uint64_t flush_va, bool is_mec, enum radv_cmd_flush_bits flush_bits, in si_cs_emit_cache_flush() argument
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| D | radv_private.h | 1683 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, bool is_mec,
1691 uint32_t *fence_ptr, uint64_t va, bool is_mec,
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| D | radv_device.c | 4597 const bool is_mec = queue->qf == RADV_QUEUE_COMPUTE && gfx_level >= GFX7; in radv_update_preamble_cs() local
4609 si_cs_emit_cache_flush(cs, gfx_level, NULL, 0, is_mec, flush_bits, &sqtt_flush_bits, 0); in radv_update_preamble_cs()
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