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Searched refs:lane (Results 1 – 25 of 91) sorted by relevance

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/third_party/typescript/src/debug/
Ddbg.ts186 lane: number;
272 lane: -1,
282 …links[id] = graphNode = { id, flowNode, edges: [], text: "", lane: -1, endLane: -1, level: -1, cir…
332 function computeLanes(node: FlowGraphNode, lane: number) {
333 if (node.lane === -1) {
334 node.lane = lane;
335 node.endLane = lane;
338 if (i > 0) lane++;
340 computeLanes(child, lane);
342 lane = child.endLane;
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/third_party/python/Modules/_sha3/kcp/
DKeccakP-1600-opt64.c98 UINT64 lane; in KeccakP1600_AddBytesInLane() local
102 lane = data[0]; in KeccakP1600_AddBytesInLane()
104 lane = 0; in KeccakP1600_AddBytesInLane()
105 memcpy(&lane, data, length); in KeccakP1600_AddBytesInLane()
107 lane <<= offset*8; in KeccakP1600_AddBytesInLane()
109 UINT64 lane = 0; in KeccakP1600_AddBytesInLane()
112 lane |= ((UINT64)data[i]) << ((i+offset)*8); in KeccakP1600_AddBytesInLane()
114 ((UINT64*)state)[lanePosition] ^= lane; in KeccakP1600_AddBytesInLane()
164 UINT64 lane = (UINT64)curData[0] in KeccakP1600_AddLanes()
172 ((UINT64*)state)[i] ^= lane; in KeccakP1600_AddLanes()
[all …]
DKeccakSponge.inc58 /* fast lane: whole lane rate */
179 /* fast lane: whole lane rate */
201 /* normal lane: using the message queue */
296 /* normal lane: using the message queue */
/third_party/optimized-routines/math/
Dv_pow.c17 for (int lane = 0; lane < v_lanes64 (); lane++) in V_NAME() local
19 f64_t sx = v_get_f64 (x, lane); in V_NAME()
20 f64_t sy = v_get_f64 (y, lane); in V_NAME()
22 v_set_f64 (&z, lane, sz); in V_NAME()
Dv_powf.c162 for (int lane = 0; lane < v_lanes32 (); lane++) in V_NAME() local
172 si = v_get_u32 (i, lane); in V_NAME()
173 siz = v_get_u32 (iz, lane); in V_NAME()
174 sk = v_get_s32 (k, lane); in V_NAME()
175 sy = v_get_f32 (y, lane); in V_NAME()
201 v_set_u32 (&cmp, lane, in V_NAME()
205 : v_get_u32 (cmp, lane)); in V_NAME()
228 v_set_f32 (&ret, lane, p); in V_NAME()
/third_party/skia/third_party/externals/spirv-cross/reference/shaders-msl-no-opt/comp/
Dsubgroups.nocompat.invalid.vk.msl21.ios.comp16 inline T spvSubgroupShuffle(T value, ushort lane)
18 return quad_shuffle(value, lane);
22 inline bool spvSubgroupShuffle(bool value, ushort lane)
24 return !!quad_shuffle((ushort)value, lane);
28 inline vec<bool, N> spvSubgroupShuffle(vec<bool, N> value, ushort lane)
30 return (vec<bool, N>)quad_shuffle((vec<ushort, N>)value, lane);
88 inline T spvQuadBroadcast(T value, uint lane)
90 return quad_broadcast(value, lane);
94 inline bool spvQuadBroadcast(bool value, uint lane)
96 return !!quad_broadcast((ushort)value, lane);
[all …]
Dsubgroups.nocompat.invalid.vk.msl22.ios.comp16 inline T spvSubgroupBroadcast(T value, ushort lane)
18 return quad_broadcast(value, lane);
22 inline bool spvSubgroupBroadcast(bool value, ushort lane)
24 return !!quad_broadcast((ushort)value, lane);
28 inline vec<bool, N> spvSubgroupBroadcast(vec<bool, N> value, ushort lane)
30 return (vec<bool, N>)quad_broadcast((vec<ushort, N>)value, lane);
117 inline T spvSubgroupShuffle(T value, ushort lane)
119 return quad_shuffle(value, lane);
123 inline bool spvSubgroupShuffle(bool value, ushort lane)
125 return !!quad_shuffle((ushort)value, lane);
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Dsubgroups.nocompat.invalid.vk.msl21.fixed-subgroup.comp16 inline T spvSubgroupBroadcast(T value, ushort lane)
18 return simd_broadcast(value, lane);
22 inline bool spvSubgroupBroadcast(bool value, ushort lane)
24 return !!simd_broadcast((ushort)value, lane);
28 inline vec<bool, N> spvSubgroupBroadcast(vec<bool, N> value, ushort lane)
30 return (vec<bool, N>)simd_broadcast((vec<ushort, N>)value, lane);
122 inline T spvSubgroupShuffle(T value, ushort lane)
124 return simd_shuffle(value, lane);
128 inline bool spvSubgroupShuffle(bool value, ushort lane)
130 return !!simd_shuffle((ushort)value, lane);
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Dsubgroups.nocompat.invalid.vk.msl23.ios.simd.comp16 inline T spvSubgroupBroadcast(T value, ushort lane)
18 return simd_broadcast(value, lane);
22 inline bool spvSubgroupBroadcast(bool value, ushort lane)
24 return !!simd_broadcast((ushort)value, lane);
28 inline vec<bool, N> spvSubgroupBroadcast(vec<bool, N> value, ushort lane)
30 return (vec<bool, N>)simd_broadcast((vec<ushort, N>)value, lane);
117 inline T spvSubgroupShuffle(T value, ushort lane)
119 return simd_shuffle(value, lane);
123 inline bool spvSubgroupShuffle(bool value, ushort lane)
125 return !!simd_shuffle((ushort)value, lane);
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Dsubgroups.nocompat.invalid.vk.msl21.comp16 inline T spvSubgroupBroadcast(T value, ushort lane)
18 return simd_broadcast(value, lane);
22 inline bool spvSubgroupBroadcast(bool value, ushort lane)
24 return !!simd_broadcast((ushort)value, lane);
28 inline vec<bool, N> spvSubgroupBroadcast(vec<bool, N> value, ushort lane)
30 return (vec<bool, N>)simd_broadcast((vec<ushort, N>)value, lane);
122 inline T spvSubgroupShuffle(T value, ushort lane)
124 return simd_shuffle(value, lane);
128 inline bool spvSubgroupShuffle(bool value, ushort lane)
130 return !!simd_shuffle((ushort)value, lane);
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/third_party/skia/third_party/externals/spirv-cross/reference/shaders-msl-no-opt/frag/
Dsubgroups.nocompat.invalid.vk.msl22.frag14 inline T spvSubgroupBroadcast(T value, ushort lane)
16 return simd_broadcast(value, lane);
20 inline bool spvSubgroupBroadcast(bool value, ushort lane)
22 return !!simd_broadcast((ushort)value, lane);
26 inline vec<bool, N> spvSubgroupBroadcast(vec<bool, N> value, ushort lane)
28 return (vec<bool, N>)simd_broadcast((vec<ushort, N>)value, lane);
120 inline T spvSubgroupShuffle(T value, ushort lane)
122 return simd_shuffle(value, lane);
126 inline bool spvSubgroupShuffle(bool value, ushort lane)
128 return !!simd_shuffle((ushort)value, lane);
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/third_party/mesa3d/src/panfrost/bifrost/valhall/
Dvalhall.py103 …halfswizzle = False, widen = False, lanes = False, combine = False, lane = None, absneg = False, n… argument
113 self.lane = lane
130 if lane:
131 self.offset['lane'] = self.lane
163 self.lane = False
226 lane = el.get('lane', None)
227 if lane == "true":
228 lane = 38 if i == 0 else 36
229 elif lane is not None:
230 lane = int(lane)
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Dasm.py245 elif src.lane and mod in enums[f'lane_{src.size}_bit'].bare_values:
268 die_if(not src.lane, "Instruction doesn't take a lane")
272 encoded |= (val << src.lane)
Dvalhall.h79 bool lane : 1; member
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrNEON.td256 // Register list of one D register, with byte lane subscripting.
266 // ...with half-word lane subscripting.
276 // ...with word lane subscripting.
287 // Register list of two D registers with byte lane subscripting.
297 // ...with half-word lane subscripting.
307 // ...with word lane subscripting.
317 // Register list of two Q registers with half-word lane subscripting.
327 // ...with word lane subscripting.
339 // Register list of three D registers with byte lane subscripting.
349 // ...with half-word lane subscripting.
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/third_party/skia/third_party/externals/swiftshader/src/Pipeline/
DSpirvShaderDebugger.cpp57 sw::vec<T, N> operator[](int lane) const in operator []()
62 out[i] = elements[i][lane]; in operator []()
72 const T &operator[](int lane) const { return data[lane]; } in operator []()
266 for(int lane = 0; lane < sw::SIMD::Width; lane++) in get() local
268 auto laneN = laneName(lane); in get()
1073 inline Memory dref(int lane) const;
1172 Shared(debug::LocalVariable const *const variable, State const *const state, int const lane) in Shared()
1175 , lane(lane) in Shared()
1182 int const lane; member
1185 LocalVariableValue(debug::LocalVariable *variable, State const *const state, int lane);
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/third_party/mesa3d/src/nouveau/codegen/
Dnv50_ir_lowering_gm107.cpp141 Value *lane = bld.mkImm(l); in handleManualTXD() local
146 bld.mkOp3(OP_SHFL, TYPE_F32, arr, i->getSrc(0), lane, quad); in handleManualTXD()
148 bld.mkOp3(OP_SHFL, TYPE_F32, shadow, i->getSrc(array + dim + indirect), lane, quad); in handleManualTXD()
153 bld.mkOp3(OP_SHFL, TYPE_F32, crd[c], i->getSrc(c + array), lane, quad); in handleManualTXD()
158 bld.mkOp3(OP_SHFL, TYPE_F32, tmp, i->dPdx[c].get(), lane, quad); in handleManualTXD()
166 bld.mkOp3(OP_SHFL, TYPE_F32, tmp, i->dPdy[c].get(), lane, quad); in handleManualTXD()
/third_party/mesa3d/src/panfrost/bifrost/
Dbi_lower_divergent_indirects.c89 nir_ssa_def *lane = nir_load_subgroup_invocation(b); in bi_lower_divergent_indirects_impl() local
101 nir_push_if(b, nir_ieq_imm(b, lane, i)); in bi_lower_divergent_indirects_impl()
/third_party/ffmpeg/libavfilter/x86/
Dvf_hflip.asm51 vpermq m1, [srcq + xq - mmsize + %3], 0x4e; flip each lane at load
52 vpermq m2, [srcq + xq - 2 * mmsize + %3], 0x4e; flip each lane at load
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DREADME_ALTIVEC.txt325 big-endian lane 0, using xscvspdpn to produce a double-precision
327 double-precision lane 0, and reinterpreting lane 0 as an FPR or
334 element into big-endian lane 1, using a direct move to a GPR, and
338 element into big-endian lane 3, using a direct move to a GPR, and
342 element into big-endian lane 7, using a direct move to a GPR, and
/third_party/flutter/flutter/examples/flutter_gallery/ios/fastlane/
DFastfile18 # to build the app using the Flutter toolchain. This lane is meant to only
24 lane :build_and_deploy_testflight do |options|
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenDAGISel.inc6046 /* 12371*/ OPC_RecordChild1, // #3 = $lane
6059 …n, (ARMvduplane:{ *:[v4i16] } DPR_8:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$lane))) - Complexity = 12
6060 …} DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR_8:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$lane)
6068 …n, (ARMvduplane:{ *:[v8i16] } DPR_8:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$lane))) - Complexity = 12
6069 …} QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, DPR_8:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$lane)
6073 /* 12432*/ OPC_RecordChild1, // #3 = $lane
6086 …(ARMvduplane:{ *:[v2i32] } DPR_VFP2:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$lane))) - Complexity = 12
6087 …PR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR_VFP2:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$lane)
6095 …(ARMvduplane:{ *:[v4i32] } DPR_VFP2:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$lane))) - Complexity = 12
6096 …PR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, DPR_VFP2:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$lane)
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SchedThunderX2T99.td1588 // ASIMD load, 1 element, one lane, B/H/S
1589 // ASIMD load, 1 element, one lane, D
1609 // ASIMD load, 2 element, one lane, B/H
1610 // ASIMD load, 2 element, one lane, S
1611 // ASIMD load, 2 element, one lane, D
1633 // ASIMD load, 3 element, one lane, S
1634 // ASIMD load, 3 element, one lane, D
1656 // ASIMD load, 4 element, one lane, B/H
1657 // ASIMD load, 4 element, one lane, S
1658 // ASIMD load, 4 element, one lane, D
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/third_party/flutter/flutter/examples/flutter_gallery/android/fastlane/
DFastfile11 lane :deploy_play_store do
/third_party/vk-gl-cts/external/vulkancts/modules/vulkan/reconvergence/
DvktReconvergenceTests.cpp1925 for (deUint32 lane = 0; lane < invocationStride; ++lane) in iterate() local
1927 deUint32 resLoc = lane + invocationStride, refLoc = lane + invocationStride; in iterate()
1939 deUint64 expectedResult = m_data.isElect() ? ((lane % subgroupSize) == 0 ? 2 : 1) in iterate()
1948 firstFail[lane] = refLoc; in iterate()
1949 …log << tcu::TestLog::Message << "lane " << lane << " first mismatch at " << firstFail[lane] << tcu… in iterate()

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