Home
last modified time | relevance | path

Searched refs:lanes (Results 1 – 25 of 63) sorted by relevance

123

/third_party/mesa3d/src/panfrost/bifrost/
Dbi_lower_divergent_indirects.c90 unsigned *lanes = data; in bi_lower_divergent_indirects_impl() local
100 for (unsigned i = 0; i < (*lanes); ++i) { in bi_lower_divergent_indirects_impl()
123 bi_lower_divergent_indirects(nir_shader *shader, unsigned lanes) in bi_lower_divergent_indirects() argument
127 nir_metadata_none, &lanes); in bi_lower_divergent_indirects()
/third_party/mesa3d/src/panfrost/bifrost/valhall/
Dvalhall.py103 …halfswizzle = False, widen = False, lanes = False, combine = False, lane = None, absneg = False, n… argument
112 self.lanes = lanes
127 if widen or lanes or halfswizzle:
162 self.lanes = False
203 if len(srcs) == 3 and (srcs[1].widen or srcs[1].lanes):
238 lanes = el.get('lanes', False),
Dva_lower_constants.c146 if (!staging && (info.widen || info.lanes) && in va_resolve_constant()
210 } else if (info.size == VA_SIZE_8 && info.lanes) { in va_lower_constants()
Dvalhall.h80 bool lanes : 1; member
Dasm.py240 elif mod in enums[f'swizzles_{src.size}_bit'].bare_values and (src.widen or src.lanes):
274 die_if(not src.lanes, "Instruction doesn't take a lane")
/third_party/mesa3d/src/nouveau/codegen/
Dnv50_ir_lowering_gm107.cpp161 add->lanes = 1; /* abused for .ndv */ in handleManualTXD()
169 add->lanes = 1; /* abused for .ndv */ in handleManualTXD()
209 mov->lanes = 1 << l; in handleManualTXD()
248 insn->lanes = 0; /* abused for !.ndv */ in handleDFDX()
Dnv50_ir_emit_nv50.cpp631 code[1] = 0x00200000 | (i->lanes << 14); in emitLOAD()
651 code[1] = 0x00200000 | (i->lanes << 14); in emitLOAD()
798 code[1] |= (i->lanes << 14); in emitMOV()
2112 emitQUADOP(insn, insn->lanes, insn->subOp); in emitInstruction()
2187 if (i->join || i->lanes != 0xf || i->exit) in getMinEncodingSize()
Dnv50_ir.cpp581 lanes = 0xf; in init()
767 i->lanes = lanes; in clone()
Dnv50_ir_emit_gk110.cpp2365 code[0] = 0x00000002 | (i->lanes << 14); in emitMOV()
2379 code[1] |= i->lanes << 10; in emitMOV()
2692 emitQUADOP(insn, insn->subOp, insn->lanes); in emitInstruction()
/third_party/typescript/src/debug/
Ddbg.ts398 const lanes: string[] = fill(Array(laneCount), ""); constant
442 for (let lane = 0; lane < lanes.length; lane++) {
463 return `\n${lanes.join("\n")}\n`;
466 lanes[lane] += text;
/third_party/mesa3d/src/amd/compiler/
DREADME.md17 …m is achieved by executing the shader on several waves, and each wave has several lanes (32 or 64).
19 otherwise when some lanes take one path while other lanes take a different path, it's divergent.
24 so in case of divergent control flow, the GPU must execute both code paths, each with some lanes di…
71 …lanes*) are active. The value of `exec` has to change in divergent branches, loops, etc. and it ne…
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SchedThunderX2T99.td1594 // ASIMD load, 1 element, all lanes, D-form, B/H/S
1595 // ASIMD load, 1 element, all lanes, D-form, D
1596 // ASIMD load, 1 element, all lanes, Q-form
1616 // ASIMD load, 2 element, all lanes, D-form, B/H/S
1617 // ASIMD load, 2 element, all lanes, D-form, D
1618 // ASIMD load, 2 element, all lanes, Q-form
1639 // ASIMD load, 3 element, all lanes, D-form, B/H/S
1640 // ASIMD load, 3 element, all lanes, D-form, D
1641 // ASIMD load, 3 element, all lanes, Q-form, B/H/S
1642 // ASIMD load, 3 element, all lanes, Q-form, D
[all …]
DAArch64Schedule.td85 // Read the unwritten lanes of the VLD's destination registers.
DAArch64RegisterInfo.td510 class TypedVecListAsmOperand<int count, string vecty, int lanes, int eltsize>
512 let Name = "TypedVectorList" # count # "_" # lanes # eltsize;
515 = "isTypedVectorList<RegKind::NeonVector, " # count # ", " # lanes # ", " # eltsize # ">";
519 class TypedVecListRegOperand<RegisterClass Reg, int lanes, string eltsize>
520 : RegisterOperand<Reg, "printTypedVectorList<" # lanes # ", '"
DAArch64CallingConvention.td35 // their lanes are in a consistent order.
134 // their lanes are in a consistent order.
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrSIMD.td218 // Shuffle lanes: shuffle
273 // Swizzle lanes: v8x16.swizzle
286 // Create vector with identical lanes: splat
315 // scalar_to_vector leaves high lanes undefined, so can be a splat
329 // Accessing lanes
617 // All lanes true: all_true
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
DIntrinsicsAMDGPU.td1370 llvm_i32_ty // returned by all lanes other than the selected one
1487 // Given a value, copies it while setting all the inactive lanes to a given
1488 // value. Note that OpenGL helper lanes are considered active, so if the
1494 LLVMMatchType<0>], // value for the inactive lanes to take
1583 // the lanes to read from.
DIntrinsicsARM.td662 // Vector load N-element structure to all lanes.
1034 // has two additional parameters: inactive (the value for inactive lanes, can
1095 // * exchange - the instruction exchanges successive even and odd lanes of
/third_party/ffmpeg/libavcodec/x86/
Dcelt_pvq_search.asm129 …VPBROADCASTD m2, xm2 ; m2=i (all lanes get same values, we add the offset-per-lane, lat…
/third_party/skia/third_party/externals/swiftshader/src/Pipeline/
DSpirvShaderDebugger.cpp1342 PerLaneVariables lanes; member
2173 auto laneLocals = std::make_shared<vk::dbg::Struct>("Lane", globals.lanes[lane]); in Data()
2388 locals[lane]->extend(globals.lanes[lane]); in getOrCreateLocals()
2406 globals.lanes[lane]->put(name, makeDbgValue(simd[lane])); in buildGlobal()
2444 globals.lanes[lane] = vc; in buildGlobals()
/third_party/skia/third_party/externals/spirv-cross/reference/shaders-msl-no-opt/frag/
Dsubgroups.nocompat.invalid.vk.msl22.frag55 // 128 lanes in an SIMD-group.
/third_party/skia/third_party/externals/spirv-cross/reference/shaders-msl-no-opt/comp/
Dsubgroups.nocompat.invalid.vk.msl21.fixed-subgroup.comp57 // 128 lanes in an SIMD-group.
Dsubgroups.nocompat.invalid.vk.msl21.comp57 // 128 lanes in an SIMD-group.
/third_party/python/Modules/_sha3/kcp/
DKeccakP-1600-64.macros45 /* --- 64-bit lanes mapped to 64-bit words */
163 /* --- 64-bit lanes mapped to 64-bit words */
258 /* --- 64-bit lanes mapped to 64-bit words */
376 /* --- 64-bit lanes mapped to 64-bit words */
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMScheduleA57.td1282 // ASIMD load, 1 element, one lane and all lanes: 8cyc "L, F0/F1"
1299 // ASIMD load, 2 element, one lane and all lanes: 8cyc "L, F0/F1"
1346 // ASIMD load, 3 element, all lanes: 8cyc "L, F0/F1"
1392 // ASIMD load, 4 element, all lanes: 8cyc "L, F0/F1"

123