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Searched refs:num_temps (Results 1 – 25 of 25) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/vc4/
Dvc4_register_allocate.c252 struct node_to_temp_map map[c->num_temps]; in vc4_register_allocate()
253 uint32_t temp_to_node[c->num_temps]; in vc4_register_allocate()
254 uint8_t class_bits[c->num_temps]; in vc4_register_allocate()
255 struct qpu_reg *temp_registers = calloc(c->num_temps, in vc4_register_allocate()
265 for (uint32_t i = 0; i < c->num_temps; i++) in vc4_register_allocate()
271 c->num_temps); in vc4_register_allocate()
278 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
282 qsort(map, c->num_temps, sizeof(map[0]), node_to_temp_priority); in vc4_register_allocate()
283 for (uint32_t i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
302 for (int i = 0; i < c->num_temps; i++) { in vc4_register_allocate()
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Dvc4_qir_live_variables.c288 int bitset_words = BITSET_WORDS(c->num_temps); in qir_calculate_live_intervals()
295 c->temp_start = rzalloc_array(c, int, c->num_temps); in qir_calculate_live_intervals()
296 c->temp_end = rzalloc_array(c, int, c->num_temps); in qir_calculate_live_intervals()
298 for (int i = 0; i < c->num_temps; i++) { in qir_calculate_live_intervals()
315 qir_compute_start_end(c, c->num_temps); in qir_calculate_live_intervals()
319 for (int i = 0; i < c->num_temps; i++) in qir_calculate_live_intervals()
325 for (int j = 0; j < c->num_temps; j++) { in qir_calculate_live_intervals()
Dvc4_qir_validate.c38 bool already_assigned[c->num_temps]; in qir_validate()
49 for (int i = 0; i < c->num_temps; i++) { in qir_validate()
59 if (inst->dst.index >= c->num_temps) in qir_validate()
113 if (src.index >= c->num_temps) in qir_validate()
Dvc4_opt_copy_propagation.c162 for (int i = 0; i < c->num_temps; i++) { in apply_kills()
178 movs = ralloc_array(c, struct qinst *, c->num_temps); in qir_opt_copy_propagation()
186 memset(movs, 0, sizeof(struct qinst *) * c->num_temps); in qir_opt_copy_propagation()
Dvc4_qir_schedule.c279 c->num_temps); in calculate_forward_deps()
399 c->num_temps); in calculate_reverse_deps()
681 state->temp_writes = rzalloc_array(state, uint32_t, c->num_temps); in qir_schedule_instructions_block()
683 BITSET_WORDS(c->num_temps)); in qir_schedule_instructions_block()
Dvc4_qir.c510 for (int i = 0; i < c->num_temps; i++) { in qir_dump()
532 for (int i = 0; i < c->num_temps; i++) { in qir_dump()
572 reg.index = c->num_temps++; in qir_get_temp()
575 if (c->num_temps > c->defs_array_size) { in qir_get_temp()
Dvc4_opt_vpm.c45 uint32_t use_count[c->num_temps]; in qir_opt_vpm()
Dvc4_opt_coalesce_ff_writes.c42 uint32_t use_count[c->num_temps]; in qir_opt_coalesce_ff_writes()
Dvc4_opt_dead_code.c88 bool *used = calloc(c->num_temps, sizeof(bool)); in qir_opt_dead_code()
Dvc4_qir.h466 uint32_t num_temps; member
/third_party/mesa3d/src/broadcom/compiler/
Dvir_register_allocate.c86 assert(temp < c->num_temps && temp < c->nodes.alloc_count); in choose_reg_class_for_temp()
231 float spill_costs[c->num_temps]; in v3d_choose_spill_node()
235 for (unsigned i = 0; i < c->num_temps; i++) in v3d_choose_spill_node()
313 for (unsigned i = 0; i < c->num_temps; i++) { in v3d_choose_spill_node()
326 if (c->num_temps < c->nodes.alloc_count) in ensure_nodes()
365 int start_num_temps = c->num_temps; in v3d_setup_spill_base()
387 for (int i = start_num_temps; i < c->num_temps; i++) { in v3d_setup_spill_base()
545 c->spill_start_num_temps = c->num_temps; in v3d_spill_reg()
719 for (int i = c->spill_start_num_temps; i < c->num_temps; i++) in v3d_spill_reg()
741 for (uint32_t i = 0; i < c->num_temps; i++) { in v3d_spill_reg()
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Dvir_live_variables.c152 rzalloc_array(c, struct partial_update_state, c->num_temps); in vir_setup_def_use()
159 sizeof(struct partial_update_state) * c->num_temps); in vir_setup_def_use()
298 int bitset_words = BITSET_WORDS(c->num_temps); in vir_calculate_live_intervals()
315 c->temp_start = rzalloc_array(c, int, c->num_temps); in vir_calculate_live_intervals()
316 c->temp_end = rzalloc_array(c, int, c->num_temps); in vir_calculate_live_intervals()
318 for (int i = 0; i < c->num_temps; i++) { in vir_calculate_live_intervals()
340 vir_compute_start_end(c, c->num_temps); in vir_calculate_live_intervals()
Dvir_opt_copy_propagate.c215 for (int i = 0; i < c->num_temps; i++) { in apply_kills()
231 movs = ralloc_array(c, struct qinst *, c->num_temps); in vir_opt_copy_propagate()
239 memset(movs, 0, sizeof(struct qinst *) * c->num_temps); in vir_opt_copy_propagate()
Dvir_dump.c374 for (int i = 0; i < c->num_temps; i++) { in vir_dump()
383 for (int i = 0; i < c->num_temps; i++) { in vir_dump()
407 for (int i = 0; i < c->num_temps; i++) { in vir_dump()
Dvir_opt_dead_code.c181 bool *used = calloc(c->num_temps, sizeof(bool)); in vir_opt_dead_code()
Dvir.c338 reg.index = c->num_temps++; in vir_get_temp()
340 if (c->num_temps > c->defs_array_size) { in vir_get_temp()
1065 for (int t = 0; t < c->num_temps; t++) { in vir_get_max_temps()
Dv3d_compiler.h854 uint32_t num_temps; member
/third_party/mesa3d/src/gallium/auxiliary/tgsi/
Dtgsi_two_side.c53 uint num_temps; member
90 ts->num_temps = MAX2(ts->num_temps, range_end); in xform_decl()
127 decl.Range.First = ts->num_temps; in emit_prolog()
128 decl.Range.Last = ts->num_temps + num_colors - 1; in emit_prolog()
130 ts->new_colors[0] = ts->num_temps; in emit_prolog()
131 ts->new_colors[1] = ts->num_temps + 1; in emit_prolog()
/third_party/mesa3d/src/gallium/drivers/etnaviv/
Detnaviv_shader.c73 printf("num temps: %i\n", shader->num_temps); in etna_dump_shader()
213 VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS(MAX2(fs->num_temps, link.num_varyings + 1)); in etna_link_shaders()
222 VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS(MAX2(fs->num_temps, link.num_varyings + 2)); in etna_link_shaders()
313 unsigned num_temps, cur_temp, num_vs_inputs; in etna_shader_update_vs_inputs() local
328 cur_temp = vs->num_temps; in etna_shader_update_vs_inputs()
329 num_temps = num_vs_inputs - vs->infile.num_reg + cur_temp; in etna_shader_update_vs_inputs()
334 VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS(num_temps); in etna_shader_update_vs_inputs()
389 v->num_temps, in dump_shader_info()
Detnaviv_compiler.h103 unsigned num_temps; member
Detnaviv_compiler_nir.c881 emit_shader(struct etna_compile *c, unsigned *num_temps, unsigned *num_consts) in emit_shader() argument
985 *num_temps = etna_ra_finish(c); in emit_shader()
1004 if (v->num_temps > specs->max_registers) { in etna_compile_check_limits()
1005 DBG("Number of registers (%d) exceeds maximum %d", v->num_temps, in etna_compile_check_limits()
1186 ASSERTED bool ok = emit_shader(c, &v->num_temps, &num_consts); in etna_compile_shader()
/third_party/mesa3d/src/gallium/drivers/r600/sb/
Dsb_ra_init.cpp53 unsigned num_temps; member in r600_sb::regbits
57 regbits(unsigned num_temps) : dta(), num_temps(num_temps) {} in regbits() argument
58 regbits(unsigned num_temps, unsigned value) : num_temps(num_temps) in regbits() argument
61 regbits(shader &sh, val_set &vs) : num_temps(sh.get_ctx().alu_temp_gprs) in regbits()
161 assert(bit < ((MAX_GPR - num_temps) << 2)); in find_free_bit()
171 for (unsigned a = 0; a < MAX_GPR - num_temps; ++a) { in find_free_array()
/third_party/mesa3d/src/gallium/auxiliary/nir/
Dnir_to_tgsi.c100 unsigned num_temps; member
119 return ureg_dst_register(TGSI_FILE_TEMPORARY, c->num_temps++); in ntt_temp()
285 state->blocks[i].def = rzalloc_array(state->blocks, uint8_t, c->num_temps); in ntt_live_reg_setup_def_use()
286 state->blocks[i].defin = rzalloc_array(state->blocks, uint8_t, c->num_temps); in ntt_live_reg_setup_def_use()
287 state->blocks[i].defout = rzalloc_array(state->blocks, uint8_t, c->num_temps); in ntt_live_reg_setup_def_use()
288 state->blocks[i].use = rzalloc_array(state->blocks, uint8_t, c->num_temps); in ntt_live_reg_setup_def_use()
289 state->blocks[i].livein = rzalloc_array(state->blocks, uint8_t, c->num_temps); in ntt_live_reg_setup_def_use()
290 state->blocks[i].liveout = rzalloc_array(state->blocks, uint8_t, c->num_temps); in ntt_live_reg_setup_def_use()
361 c->liveness = rzalloc_array(c, struct ntt_reg_interval, c->num_temps); in ntt_live_regs()
368 for (int i = 0; i < c->num_temps; i++) in ntt_live_regs()
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/third_party/mesa3d/src/imagination/vulkan/pds/
Dpvr_pds.c281 pvr_pds_get_temps(uint32_t *next_temp, uint32_t num_temps, uint32_t *count) in pvr_pds_get_temps() argument
288 if (num_temps & 1) in pvr_pds_get_temps()
294 *count += temp + num_temps - *next_temp; in pvr_pds_get_temps()
297 *next_temp = temp + num_temps; in pvr_pds_get_temps()
299 assert((temp + num_temps) <= in pvr_pds_get_temps()
/third_party/mesa3d/src/gallium/drivers/svga/
Dsvga_tgsi_vgpu10.c5832 unsigned num_temps = emit->temp_arrays[i].size; in emit_temporaries_declaration() local
5834 if (num_temps > 0) { in emit_temporaries_declaration()
5843 emit_dword(emit, num_temps); in emit_temporaries_declaration()
5847 total_temps += num_temps; in emit_temporaries_declaration()