/third_party/flutter/skia/third_party/externals/spirv-tools/source/opt/ |
D | instruction.h | 250 for (auto& opnd : operands_) { in ForEachInId() 251 switch (opnd.type) { in ForEachInId() 256 if (spvIsIdType(opnd.type)) f(&opnd.words[0]); in ForEachInId() 264 for (const auto& opnd : operands_) { in ForEachInId() local 265 switch (opnd.type) { in ForEachInId() 270 if (spvIsIdType(opnd.type)) f(&opnd.words[0]); in ForEachInId()
|
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/ |
D | BPFMIPeephole.cpp | 85 MachineOperand &opnd = CopyMI->getOperand(1); in isCopyFrom32Def() local 87 if (!opnd.isReg()) in isCopyFrom32Def() 93 Register Reg = opnd.getReg(); in isCopyFrom32Def() 110 MachineOperand &opnd = PhiMI->getOperand(i); in isPhiFrom32Def() local 112 if (!opnd.isReg()) in isPhiFrom32Def() 115 MachineInstr *PhiDef = MRI->getVRegDef(opnd.getReg()); in isPhiFrom32Def() 466 MachineOperand &opnd = DefMI->getOperand(i); in eliminateTruncSeq() local 467 if (!opnd.isReg()) { in eliminateTruncSeq() 472 MachineInstr *PhiDef = MRI->getVRegDef(opnd.getReg()); in eliminateTruncSeq()
|
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-subzero/lib/Support/ |
D | regex2.h | 72 #define SOP(op, opnd) ((op)|(opnd)) argument
|
D | regcomp.c | 1347 doemit(struct parse *p, sop op, size_t opnd) in doemit() argument 1354 assert(opnd < 1<<OPSHIFT); in doemit() 1362 p->strip[p->slen++] = SOP(op, opnd); in doemit() 1369 doinsert(struct parse *p, sop op, size_t opnd, sopno pos) in doinsert() argument 1380 EMIT(op, opnd); /* do checks, ensure space */ in doinsert()
|
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Support/ |
D | regex2.h | 75 #define SOP(op, opnd) ((op)|(opnd)) argument
|
D | regcomp.c | 1475 doemit(struct parse *p, sop op, size_t opnd) in doemit() argument 1482 assert(opnd < 1<<OPSHIFT); in doemit() 1490 p->strip[p->slen++] = SOP(op, opnd); in doemit() 1497 doinsert(struct parse *p, sop op, size_t opnd, sopno pos) in doinsert() argument 1508 EMIT(op, opnd); /* do checks, ensure space */ in doinsert()
|
/third_party/spirv-tools/source/opt/ |
D | value_number_table.cpp | 232 const auto& opnd = inst.GetInOperand(i); in operator ()() local 233 for (uint32_t word : opnd.words) { in operator ()()
|
/third_party/skia/third_party/externals/swiftshader/third_party/SPIRV-Tools/source/opt/ |
D | value_number_table.cpp | 232 const auto& opnd = inst.GetInOperand(i); in operator ()() local 233 for (uint32_t word : opnd.words) { in operator ()()
|
/third_party/skia/third_party/externals/spirv-tools/source/opt/ |
D | value_number_table.cpp | 232 const auto& opnd = inst.GetInOperand(i); in operator ()() local 233 for (uint32_t word : opnd.words) { in operator ()()
|
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
D | X86FixupLEAs.cpp | 244 MachineOperand &opnd = MI.getOperand(i); in usesRegister() local 245 if (opnd.isReg() && opnd.getReg() == p.getReg()) { in usesRegister() 246 if (opnd.isDef()) in usesRegister()
|
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
D | Mips32r6InstrInfo.td | 372 class BC_DESC_BASE<string instr_asm, DAGOperand opnd> : BRANCH_DESC_BASE, 374 dag InOperandList = (ins opnd:$offset); 382 class CMP_BC_DESC_BASE<string instr_asm, DAGOperand opnd, 385 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset); 394 class CMP_CBR_EQNE_Z_DESC_BASE<string instr_asm, DAGOperand opnd, 397 dag InOperandList = (ins GPROpnd:$rs, opnd:$offset); 406 class CMP_CBR_RT_Z_DESC_BASE<string instr_asm, DAGOperand opnd, 409 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset); 476 class JMP_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd, 480 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
|
D | MipsInstrInfo.td | 1469 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op, 1471 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset), 1482 class CBranchLikely<string opstr, DAGOperand opnd, RegisterOperand RO> : 1483 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset), 1492 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op, 1494 InstSE<(outs), (ins RO:$rs, opnd:$offset), 1505 class CBranchZeroLikely<string opstr, DAGOperand opnd, RegisterOperand RO> : 1506 InstSE<(outs), (ins RO:$rs, opnd:$offset), 1530 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator, 1532 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"), [all …]
|
D | MicroMipsInstrInfo.td | 198 class CompactBranchMM<string opstr, DAGOperand opnd, PatFrag cond_op, 200 InstSE<(outs), (ins RO:$rs, opnd:$offset), 475 class CBranchZeroMM<string opstr, DAGOperand opnd, RegisterOperand RO> : 476 MicroMipsInst16<(outs), (ins RO:$rs, opnd:$offset), 486 class JumpLinkMM<string opstr, DAGOperand opnd> : 487 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"), 496 class BranchCompareToZeroLinkMM<string opstr, DAGOperand opnd, 498 InstSE<(outs), (ins RO:$rs, opnd:$offset),
|
D | MicroMips32r6InstrInfo.td | 272 class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd, 275 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset); 321 class CMP_CBR_2R_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd, 323 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset); 352 class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd, InstrItinClass Itin> 354 dag InOperandList = (ins opnd:$offset); 468 class JMP_MMR6_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd, 472 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset); 1322 class BOVC_BNVC_MMR6_DESC_BASE<string instr_asm, Operand opnd, 1325 dag InOperandList = (ins GPROpnd:$rt, GPROpnd:$rs, opnd:$offset);
|
D | MipsInstrFPU.td | 231 class BC1F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin, 233 InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset), 244 class BC1XL_FT<string opstr, DAGOperand opnd, InstrItinClass Itin> : 245 InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset),
|
D | MipsDSPInstrInfo.td | 531 class BPOSGE32_DESC_BASE<string instr_asm, DAGOperand opnd, 534 dag InOperandList = (ins opnd:$offset);
|
D | Mips64InstrInfo.td | 488 class CBranchBitNum<string opstr, DAGOperand opnd, PatFrag cond_op, 490 InstSE<(outs), (ins RO:$rs, ImmOp:$p, opnd:$offset),
|
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
D | RISCVInstrInfoC.td | 219 RegisterClass cls, DAGOperand opnd> 220 : RVInst16CI<funct3, 0b10, (outs cls:$rd), (ins SP:$rs1, opnd:$imm), 225 RegisterClass cls, DAGOperand opnd> 226 : RVInst16CSS<funct3, 0b10, (outs), (ins cls:$rs2, SP:$rs1, opnd:$imm), 231 RegisterClass cls, DAGOperand opnd> 232 : RVInst16CL<funct3, 0b00, (outs cls:$rd), (ins GPRC:$rs1, opnd:$imm), 237 RegisterClass cls, DAGOperand opnd> 238 : RVInst16CS<funct3, 0b00, (outs), (ins cls:$rs2, GPRC:$rs1, opnd:$imm),
|
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
D | VOP2Instructions.td | 198 string OpName, string opnd> : 199 InstAlias <OpName#" "#!subst("vcc", opnd, ps.Pfl.Asm32), 239 class VOP2eInstAlias <VOP2_Pseudo ps, Instruction inst, string opnd> : 240 InstAlias <ps.OpName#" "#ps.Pfl.Asm32#", "#opnd,
|
/third_party/mesa3d/src/nouveau/codegen/ |
D | nv50_ir_peephole.cpp | 377 bool opnd(Instruction *i, ImmediateValue&, int s); 429 if (opnd(i, src0, 0)) in visit() 433 if (opnd(i, src1, 1)) in visit() 772 opnd(i, src1, 1); in expr() 1052 ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s) in opnd() function in nv50_ir::ConstantFolding
|
/third_party/toybox/toys/pending/ |
D | bc.c | 5259 BcResult *opnd; in bc_program_builtin() local 5264 s = bc_program_operand(p, &opnd, &num, 0); in bc_program_builtin() 5277 if (opnd->t == BC_RESULT_ARRAY) in bc_program_builtin()
|