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/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_build_pm4.h76 #define radeon_set_config_reg_seq(reg, num) do { \ argument
77 SI_CHECK_SHADOWED_REGS(reg, num); \
78 assert((reg) < SI_CONTEXT_REG_OFFSET); \
80 radeon_emit(((reg) - SI_CONFIG_REG_OFFSET) >> 2); \
83 #define radeon_set_config_reg(reg, value) do { \ argument
84 radeon_set_config_reg_seq(reg, 1); \
88 #define radeon_set_context_reg_seq(reg, num) do { \ argument
89 SI_CHECK_SHADOWED_REGS(reg, num); \
90 assert((reg) >= SI_CONTEXT_REG_OFFSET); \
92 radeon_emit(((reg) - SI_CONTEXT_REG_OFFSET) >> 2); \
[all …]
/third_party/gstreamer/gstplugins_good/gst/deinterlace/tvtime/
Dmmx.h275 #define mmx_i2r(op, imm, reg) \ argument
280 __asm__ __volatile__ ("movq %%" #reg ", %0" \
283 fprintf(stderr, #reg "=0x%016llx) => ", mmx_trace.q); \
284 __asm__ __volatile__ (#op " %0, %%" #reg \
287 __asm__ __volatile__ ("movq %%" #reg ", %0" \
290 fprintf(stderr, #reg "=0x%016llx\n", mmx_trace.q); \
293 #define mmx_m2r(op, mem, reg) \ argument
298 __asm__ __volatile__ ("movq %%" #reg ", %0" \
301 fprintf(stderr, #reg "=0x%016llx) => ", mmx_trace.q); \
302 __asm__ __volatile__ (#op " %0, %%" #reg \
[all …]
Dsse.h246 #define sse_i2r(op, imm, reg) \ argument
252 __asm__ __volatile__ ("movq %%" #reg ", %0" \
255 fprintf(stderr, #reg "=0x%08x%08x) => ", \
257 __asm__ __volatile__ (#op " %0, %%" #reg \
260 __asm__ __volatile__ ("movq %%" #reg ", %0" \
263 fprintf(stderr, #reg "=0x%08x%08x\n", \
267 #define sse_m2r(op, mem, reg) \ argument
273 __asm__ __volatile__ ("movq %%" #reg ", %0" \
276 fprintf(stderr, #reg "=0x%08x%08x) => ", \
278 __asm__ __volatile__ (#op " %0, %%" #reg \
[all …]
/third_party/gstreamer/gstplugins_good/gst/goom/
Dmmx.h263 #define mmx_i2r(op, imm, reg) \ argument
269 __asm__ __volatile__ ("movq %%" #reg ", %0" \
272 printf(#reg "=0x%08x%08x) => ", \
274 __asm__ __volatile__ (#op " %0, %%" #reg \
277 __asm__ __volatile__ ("movq %%" #reg ", %0" \
280 printf(#reg "=0x%08x%08x\n", \
284 #define mmx_m2r(op, mem, reg) \ argument
290 __asm__ __volatile__ ("movq %%" #reg ", %0" \
293 printf(#reg "=0x%08x%08x) => ", \
295 __asm__ __volatile__ (#op " %0, %%" #reg \
[all …]
/third_party/flutter/skia/third_party/externals/sdl/src/render/
Dmmx.h178 #define mmx_i2r(op, imm, reg) \ argument
184 __asm__ __volatile__ ("movq %%" #reg ", %0" \
187 printf(#reg "=0x%08x%08x) => ", \
189 __asm__ __volatile__ (#op " %0, %%" #reg \
192 __asm__ __volatile__ ("movq %%" #reg ", %0" \
195 printf(#reg "=0x%08x%08x\n", \
199 #define mmx_m2r(op, mem, reg) \ argument
205 __asm__ __volatile__ ("movq %%" #reg ", %0" \
208 printf(#reg "=0x%08x%08x) => ", \
210 __asm__ __volatile__ (#op " %0, %%" #reg \
[all …]
/third_party/mesa3d/src/intel/compiler/
Dbrw_reg.h407 struct brw_reg reg; in brw_reg() local
417 reg.type = type; in brw_reg()
418 reg.file = file; in brw_reg()
419 reg.negate = negate; in brw_reg()
420 reg.abs = abs; in brw_reg()
421 reg.address_mode = BRW_ADDRESS_DIRECT; in brw_reg()
422 reg.pad0 = 0; in brw_reg()
423 reg.subnr = subnr * type_sz(type); in brw_reg()
424 reg.nr = nr; in brw_reg()
432 reg.swizzle = swizzle; in brw_reg()
[all …]
Dbrw_clip_line.c46 c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++; in brw_clip_line_alloc_regs()
49 c->reg.fixed_planes = brw_vec4_grf(i, 0); in brw_clip_line_alloc_regs()
61 c->reg.vertex[j] = brw_vec4_grf(i, 0); in brw_clip_line_alloc_regs()
65 c->reg.t = brw_vec1_grf(i, 0); in brw_clip_line_alloc_regs()
66 c->reg.t0 = brw_vec1_grf(i, 1); in brw_clip_line_alloc_regs()
67 c->reg.t1 = brw_vec1_grf(i, 2); in brw_clip_line_alloc_regs()
68 c->reg.planemask = retype(brw_vec1_grf(i, 3), BRW_REGISTER_TYPE_UD); in brw_clip_line_alloc_regs()
69 c->reg.plane_equation = brw_vec4_grf(i, 4); in brw_clip_line_alloc_regs()
72 c->reg.dp0 = brw_vec1_grf(i, 0); /* fixme - dp4 will clobber r.1,2,3 */ in brw_clip_line_alloc_regs()
73 c->reg.dp1 = brw_vec1_grf(i, 4); in brw_clip_line_alloc_regs()
[all …]
Dbrw_ir_vec4.h43 src_reg(struct ::brw_reg reg);
51 explicit src_reg(const dst_reg &reg);
57 retype(src_reg reg, enum brw_reg_type type) in retype() argument
59 reg.type = type; in retype()
60 return reg; in retype()
66 add_byte_offset(backend_reg *reg, unsigned bytes) in add_byte_offset() argument
68 switch (reg->file) { in add_byte_offset()
74 reg->offset += bytes; in add_byte_offset()
75 assert(reg->offset % 16 == 0); in add_byte_offset()
78 const unsigned suboffset = reg->offset + bytes; in add_byte_offset()
[all …]
Dbrw_ir_fs.h39 fs_reg(struct ::brw_reg reg);
58 negate(fs_reg reg) in negate() argument
60 assert(reg.file != IMM); in negate()
61 reg.negate = !reg.negate; in negate()
62 return reg; in negate()
66 retype(fs_reg reg, enum brw_reg_type type) in retype() argument
68 reg.type = type; in retype()
69 return reg; in retype()
73 byte_offset(fs_reg reg, unsigned delta) in byte_offset() argument
75 switch (reg.file) { in byte_offset()
[all …]
Dbrw_clip_tri.c53 c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++; in brw_clip_tri_alloc_regs()
56 c->reg.fixed_planes = brw_vec4_grf(i, 0); in brw_clip_tri_alloc_regs()
68 c->reg.vertex[j] = brw_vec4_grf(i, 0); in brw_clip_tri_alloc_regs()
79 brw_MOV(&c->func, byte_offset(c->reg.vertex[j], delta), brw_imm_f(0)); in brw_clip_tri_alloc_regs()
83 c->reg.t = brw_vec1_grf(i, 0); in brw_clip_tri_alloc_regs()
84 c->reg.loopcount = retype(brw_vec1_grf(i, 1), BRW_REGISTER_TYPE_D); in brw_clip_tri_alloc_regs()
85 c->reg.nr_verts = retype(brw_vec1_grf(i, 2), BRW_REGISTER_TYPE_UD); in brw_clip_tri_alloc_regs()
86 c->reg.planemask = retype(brw_vec1_grf(i, 3), BRW_REGISTER_TYPE_UD); in brw_clip_tri_alloc_regs()
87 c->reg.plane_equation = brw_vec4_grf(i, 4); in brw_clip_tri_alloc_regs()
90 c->reg.dpPrev = brw_vec1_grf(i, 0); /* fixme - dp4 will clobber r.1,2,3 */ in brw_clip_tri_alloc_regs()
[all …]
Dbrw_compile_ff_gs.c64 } reg; member
90 c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++; in brw_ff_gs_alloc_regs()
94 c->reg.SVBI = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD); in brw_ff_gs_alloc_regs()
99 c->reg.vertex[j] = brw_vec4_grf(i, 0); in brw_ff_gs_alloc_regs()
103 c->reg.header = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD); in brw_ff_gs_alloc_regs()
104 c->reg.temp = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD); in brw_ff_gs_alloc_regs()
107 c->reg.destination_indices = in brw_ff_gs_alloc_regs()
133 brw_MOV(p, c->reg.header, c->reg.R0); in brw_ff_gs_initialize_header()
147 brw_MOV(p, get_element_ud(c->reg.header, 2), brw_imm_ud(dw2)); in brw_ff_gs_overwrite_header_dw2()
161 brw_AND(p, get_element_ud(c->reg.header, 2), get_element_ud(c->reg.R0, 2), in brw_ff_gs_overwrite_header_dw2_from_r0()
[all …]
/third_party/mesa3d/src/gallium/auxiliary/tgsi/
Dtgsi_sanity.c67 scan_register_key(const scan_register *reg) in scan_register_key() argument
69 unsigned key = reg->file; in scan_register_key()
70 key |= (reg->indices[0] << 4); in scan_register_key()
71 key |= (reg->indices[1] << 18); in scan_register_key()
77 fill_scan_register1d(scan_register *reg, in fill_scan_register1d() argument
80 reg->file = file; in fill_scan_register1d()
81 reg->dimensions = 1; in fill_scan_register1d()
82 reg->indices[0] = index; in fill_scan_register1d()
83 reg->indices[1] = 0; in fill_scan_register1d()
87 fill_scan_register2d(scan_register *reg, in fill_scan_register2d() argument
[all …]
/third_party/mesa3d/src/amd/vulkan/
Dradv_cs.h43 radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_config_reg_seq() argument
45 assert(reg >= SI_CONFIG_REG_OFFSET && reg < SI_CONFIG_REG_END); in radeon_set_config_reg_seq()
49 radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2); in radeon_set_config_reg_seq()
53 radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_config_reg() argument
55 radeon_set_config_reg_seq(cs, reg, 1); in radeon_set_config_reg()
60 radeon_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_context_reg_seq() argument
62 assert(reg >= SI_CONTEXT_REG_OFFSET && reg < SI_CONTEXT_REG_END); in radeon_set_context_reg_seq()
66 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2); in radeon_set_context_reg_seq()
70 radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_context_reg() argument
72 radeon_set_context_reg_seq(cs, reg, 1); in radeon_set_context_reg()
[all …]
/third_party/libunwind/src/aarch64/
DGstash_frame.c39 rs->reg.where[DWARF_CFA_REG_COLUMN], in tdep_stash_frame()
40 rs->reg.val[DWARF_CFA_REG_COLUMN], in tdep_stash_frame()
41 rs->reg.val[DWARF_CFA_OFF_COLUMN], in tdep_stash_frame()
43 rs->reg.where[FP], rs->reg.val[FP], DWARF_GET_LOC(d->loc[FP]), in tdep_stash_frame()
44 rs->reg.where[LR], rs->reg.val[LR], DWARF_GET_LOC(d->loc[LR]), in tdep_stash_frame()
45 rs->reg.where[SP], rs->reg.val[SP], DWARF_GET_LOC(d->loc[SP])); in tdep_stash_frame()
54 && (rs->reg.where[DWARF_CFA_REG_COLUMN] == DWARF_WHERE_REG) in tdep_stash_frame()
55 && (rs->reg.val[DWARF_CFA_REG_COLUMN] == FP in tdep_stash_frame()
56 || rs->reg.val[DWARF_CFA_REG_COLUMN] == SP) in tdep_stash_frame()
57 && labs(rs->reg.val[DWARF_CFA_OFF_COLUMN]) < (1 << 29) in tdep_stash_frame()
[all …]
/third_party/libunwind/src/arm/
DGstash_frame.c39 rs->reg.where[DWARF_CFA_REG_COLUMN], in tdep_stash_frame()
40 rs->reg.val[DWARF_CFA_REG_COLUMN], in tdep_stash_frame()
41 rs->reg.val[DWARF_CFA_OFF_COLUMN], in tdep_stash_frame()
43 rs->reg.where[R7], rs->reg.val[R7], DWARF_GET_LOC(d->loc[R7]), in tdep_stash_frame()
44 rs->reg.where[LR], rs->reg.val[LR], DWARF_GET_LOC(d->loc[LR]), in tdep_stash_frame()
45 rs->reg.where[SP], rs->reg.val[SP], DWARF_GET_LOC(d->loc[SP])); in tdep_stash_frame()
54 && (rs->reg.where[DWARF_CFA_REG_COLUMN] == DWARF_WHERE_REG) in tdep_stash_frame()
55 && (rs->reg.val[DWARF_CFA_REG_COLUMN] == R7 in tdep_stash_frame()
56 || rs->reg.val[DWARF_CFA_REG_COLUMN] == SP) in tdep_stash_frame()
57 && labs(rs->reg.val[DWARF_CFA_OFF_COLUMN]) < (1 << 29) in tdep_stash_frame()
[all …]
/third_party/mesa3d/src/panfrost/bifrost/valhall/test/
Dtest-lower-isel.cpp45 reg = bi_register(1); in LowerIsel()
56 bi_index reg, x, y, z; member in LowerIsel
61 CASE(bi_swz_v4i8_to(b, reg, bi_byte(reg, i)),
62 bi_iadd_v4u8_to(b, reg, bi_byte(reg, i), bi_zero(), false));
69 CASE(bi_swz_v2i16_to(b, reg, bi_swz_16(reg, i, j)),
70 bi_iadd_v2u16_to(b, reg, bi_swz_16(reg, i, j), bi_zero(), false));
93 CASE(bi_csel_i32(b, reg, reg, reg, reg, BI_CMPF_EQ), in TEST_F()
94 bi_csel_u32(b, reg, reg, reg, reg, BI_CMPF_EQ)); in TEST_F()
96 CASE(bi_csel_v2i16(b, reg, reg, reg, reg, BI_CMPF_EQ), in TEST_F()
97 bi_csel_v2u16(b, reg, reg, reg, reg, BI_CMPF_EQ)); in TEST_F()
[all …]
/third_party/musl/porting/linux/user/include/sys/
Dsspret.h21 # define SSPRET_CALC_RETCOOKIE(reg) \ argument
22 eor reg, reg, x30
24 # define SSPRET_LOAD_COOKIE(x, reg) \ argument
25 mov reg, x29
27 # define SSPRET_SETUP(x, reg) \ argument
28 SSPRET_LOAD_COOKIE(x, reg); \
29 SSPRET_CALC_RETCOOKIE(reg)
31 # define SSPRET_CHECK(x, reg) \ argument
34 subs reg, reg, x9; \
35 cbz reg, 6788f; \
[all …]
/third_party/openssl/include/crypto/
Dsparc_arch.h57 # define SPARC_PIC_THUNK(reg) \ argument
61 add %o7, reg, reg;
63 # define SPARC_PIC_THUNK_CALL(reg) \ argument
64 sethi %hi(_GLOBAL_OFFSET_TABLE_-4), reg; \
66 or reg, %lo(_GLOBAL_OFFSET_TABLE_+4), reg;
69 # define SPARC_SETUP_GOT_REG(reg) SPARC_PIC_THUNK_CALL(reg) argument
71 # define SPARC_SETUP_GOT_REG(reg) \ argument
72 sethi %hi(_GLOBAL_OFFSET_TABLE_-4), reg; \
74 or reg,%lo(_GLOBAL_OFFSET_TABLE_+4), reg; \
75 add %o7, reg, reg
[all …]
/third_party/mesa3d/src/panfrost/bifrost/test/
Dtest-optimizer.cpp46 reg = bi_register(0); in Optimizer()
58 bi_index reg; member in Optimizer
66 CASE(bi_fadd_f32_to(b, reg, bi_fabsneg_f32(b, bi_abs(x)), y), in TEST_F()
67 bi_fadd_f32_to(b, reg, bi_abs(x), y)); in TEST_F()
69 CASE(bi_fadd_f32_to(b, reg, bi_fabsneg_f32(b, bi_neg(x)), y), in TEST_F()
70 bi_fadd_f32_to(b, reg, bi_neg(x), y)); in TEST_F()
72 CASE(bi_fadd_f32_to(b, reg, bi_fabsneg_f32(b, negabsx), y), in TEST_F()
73 bi_fadd_f32_to(b, reg, negabsx, y)); in TEST_F()
75 CASE(bi_fadd_f32_to(b, reg, bi_fabsneg_f32(b, x), y), in TEST_F()
76 bi_fadd_f32_to(b, reg, x, y)); in TEST_F()
[all …]
/third_party/libffi/include/
Dffi_cfi.h14 # define cfi_def_cfa(reg, off) .cfi_def_cfa reg, off argument
15 # define cfi_def_cfa_register(reg) .cfi_def_cfa_register reg argument
18 # define cfi_offset(reg, off) .cfi_offset reg, off argument
19 # define cfi_rel_offset(reg, off) .cfi_rel_offset reg, off argument
21 # define cfi_return_column(reg) .cfi_return_column reg argument
22 # define cfi_restore(reg) .cfi_restore reg argument
23 # define cfi_same_value(reg) .cfi_same_value reg argument
24 # define cfi_undefined(reg) .cfi_undefined reg argument
36 # define cfi_def_cfa(reg, off) argument
37 # define cfi_def_cfa_register(reg) argument
[all …]
/third_party/mesa3d/src/gallium/drivers/i915/
Di915_fpc_emit.c47 i915_release_temp(struct i915_fp_compile *p, int reg) in i915_release_temp() argument
49 p->temp_flag &= ~(1 << reg); in i915_release_temp()
79 uint32_t reg = UREG(type, nr); in i915_emit_decl() local
83 return reg; in i915_emit_decl()
88 return reg; in i915_emit_decl()
92 return reg; in i915_emit_decl()
95 *(p->decl++) = (D0_DCL | D0_DEST(reg) | d0_flags); in i915_emit_decl()
102 return reg; in i915_emit_decl()
261 unsigned reg, idx; in i915_emit_const1f() local
268 for (reg = 0; reg < I915_MAX_CONSTANT; reg++) { in i915_emit_const1f()
[all …]
/third_party/libunwind/src/x86_64/
DGstash_frame.c37 rs->reg.where[DWARF_CFA_REG_COLUMN], in tdep_stash_frame()
38 rs->reg.val[DWARF_CFA_REG_COLUMN], in tdep_stash_frame()
39 rs->reg.val[DWARF_CFA_OFF_COLUMN], in tdep_stash_frame()
41 rs->reg.where[RBP], rs->reg.val[RBP], DWARF_GET_LOC(d->loc[RBP]), in tdep_stash_frame()
42 rs->reg.where[RSP], rs->reg.val[RSP], DWARF_GET_LOC(d->loc[RSP])); in tdep_stash_frame()
44 if (rs->reg.where[DWARF_CFA_REG_COLUMN] == DWARF_WHERE_EXPR && in tdep_stash_frame()
45 rs->reg.where[RBP] == DWARF_WHERE_EXPR) { in tdep_stash_frame()
49 unw_word_t cfa_addr = rs->reg.val[DWARF_CFA_REG_COLUMN]; in tdep_stash_frame()
50 unw_word_t rbp_addr = rs->reg.val[RBP]; in tdep_stash_frame()
67 && (rs->reg.where[DWARF_CFA_REG_COLUMN] == DWARF_WHERE_REG) in tdep_stash_frame()
[all …]
/third_party/mesa3d/src/gallium/drivers/freedreno/a2xx/
Dir2_ra.c59 struct ir2_reg *reg; in set_need_emit() local
74 reg = get_reg_src(ctx, src); in set_need_emit()
76 if (!instr->is_ssa && instr->reg == reg) in set_need_emit()
110 struct ir2_reg *reg; in ra_count_refs() local
132 reg = get_reg_src(ctx, src); in ra_count_refs()
134 reg->comp[swiz_get(src->swizzle, i)].ref_count++; in ra_count_refs()
140 ra_reg(struct ir2_context *ctx, struct ir2_reg *reg, int force_idx, bool export, in ra_reg() argument
146 reg->comp[i].c = i; in ra_reg()
158 for (int i = 0; i < reg->ncomp; i++) { in ra_reg()
159 if (reg->comp[i].alloc) in ra_reg()
[all …]
/third_party/mesa3d/src/compiler/nir/
Dnir_lower_regs_to_ssa.c48 nir_register *reg = src->reg.reg; in rewrite_src() local
49 struct nir_phi_builder_value *value = state->values[reg->index]; in rewrite_src()
74 nir_register *reg = nif->condition.reg.reg; in rewrite_if_condition() local
75 struct nir_phi_builder_value *value = state->values[reg->index]; in rewrite_if_condition()
91 nir_instr *instr = dest->reg.parent_instr; in rewrite_dest()
92 nir_register *reg = dest->reg.reg; in rewrite_dest() local
93 struct nir_phi_builder_value *value = state->values[reg->index]; in rewrite_dest()
97 list_del(&dest->reg.def_link); in rewrite_dest()
98 nir_ssa_dest_init(instr, dest, reg->num_components, in rewrite_dest()
99 reg->bit_size, NULL); in rewrite_dest()
[all …]
/third_party/libunwind/src/ia64/
DGregs.c31 linux_scratch_loc (struct cursor *c, unw_regnum_t reg, uint8_t *nat_bitnr) in linux_scratch_loc() argument
40 switch (reg) in linux_scratch_loc()
46 *nat_bitnr = (reg - UNW_IA64_NAT); in linux_scratch_loc()
52 addr += LINUX_SC_GR_OFF + 8 * (reg - UNW_IA64_GR); in linux_scratch_loc()
56 addr += LINUX_SC_FR_OFF + 16 * (reg - UNW_IA64_FR); in linux_scratch_loc()
78 addr += LINUX_SC_FR_OFF + 16 * (reg - UNW_IA64_FR); in linux_scratch_loc()
90 if (unw_is_fpreg (reg)) in linux_scratch_loc()
91 return IA64_FPREG_LOC (c, reg); in linux_scratch_loc()
93 return IA64_REG_LOC (c, reg); in linux_scratch_loc()
101 if ((unsigned) (reg - UNW_IA64_NAT) < 128) in linux_scratch_loc()
[all …]

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