| /third_party/libdrm/tests/tegra/ |
| D | drm-test-tegra.h | 39 #define HOST1X_OPCODE_EXTEND(subop, value) \ argument
40 ((0xe << 28) | (((subop) & 0xf) << 24) | ((value) & 0xffffff))
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/ |
| D | ARCInstrFormats.td | 246 // |B[2-0] | 0| 0| 1| 0| 1| 1| 1| 1| F|B[5-3] |C |subop |
247 class F32_SOP_RR<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
261 let Inst{5-0} = subop;
269 // |B[2-0] | 0| 0| subop| F|B[5-3] |C |A |
270 class F32_DOP_RR<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
280 let Inst{21-16} = subop;
290 // |B[2-0] | 1| 1| subop| F|B[5-3] |C |A |
291 class F32_DOP_CC_RR<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
301 let Inst{21-16} = subop;
312 // |B[2-0] | 0| 1| subop| F|B[5-3] |U6 |A |
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| D | ARCInstrInfo.td | 174 multiclass ArcSpecialDOPInst<bits<6> subop, string opasm, bit F> {
175 def _rr : F32_DOP_RR<0b00100, subop, F, (outs), (ins GPR32:$B, GPR32:$C),
179 def _ru6 : F32_DOP_RU6<0b00100, subop, F, (outs), (ins GPR32:$B, i32imm:$U6),
183 def _rlimm : F32_DOP_RLIMM<0b00100, subop, F, (outs),
190 multiclass ArcUnaryInst<bits<5> major, bits<6> subop,
192 def _rr : F32_SOP_RR<major, subop, 0, (outs GPR32:$B), (ins GPR32:$C),
195 def _f_rr : F32_SOP_RR<major, subop, 1, (outs GPR32:$B), (ins GPR32:$C),
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| /third_party/mesa3d/src/nouveau/codegen/ |
| D | nv50_ir_emit_gv100.cpp | 247 int subop = 0; in emitFRND() local
252 case ROUND_NI: subop = 0; break; in emitFRND()
253 case ROUND_MI: subop = 1; break; in emitFRND()
254 case ROUND_PI: subop = 2; break; in emitFRND()
255 case ROUND_ZI: subop = 3; break; in emitFRND()
261 case OP_FLOOR: subop = 1; break; in emitFRND()
262 case OP_CEIL : subop = 2; break; in emitFRND()
263 case OP_TRUNC: subop = 3; break; in emitFRND()
275 emitField(78, 2, subop); in emitFRND()
1584 uint8_t subop, redop = 0x00; in emitBAR() local
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| D | nv50_ir_emit_gm107.cpp | 3164 uint8_t subop; in emitBAR() local
3169 case NV50_IR_SUBOP_BAR_RED_POPC: subop = 0x02; break; in emitBAR()
3170 case NV50_IR_SUBOP_BAR_RED_AND: subop = 0x0a; break; in emitBAR()
3171 case NV50_IR_SUBOP_BAR_RED_OR: subop = 0x12; break; in emitBAR()
3172 case NV50_IR_SUBOP_BAR_ARRIVE: subop = 0x81; break; in emitBAR()
3174 subop = 0x80; in emitBAR()
3179 emitField(0x20, 8, subop); in emitBAR()
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| /third_party/mesa3d/docs/relnotes/ |
| D | 10.1.5.rst | 58 - nv50/ir: fix constant folding for OP_MUL subop HIGH
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| D | 10.1.6.rst | 104 - nv50/ir: clear subop when folding constant expressions
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| /third_party/gstreamer/gstplugins_good/gst/deinterlace/tvtime/ |
| D | sse.h | 383 #define sse_m2ri(op, mem, reg, subop) \ argument
384 __asm__ __volatile__ (#op " %0, %%" #reg ", " #subop \
388 #define sse_m2mi(op, mems, memd, xmmreg, subop) \ argument
390 #op " %1, %%xmm0, " #subop "\n\t" \
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| /third_party/skia/third_party/externals/spirv-cross/ |
| D | spirv_glsl.cpp | 9676 string subop; in build_composite_combiner() local
9693 subop += e->expression.substr(1, string::npos); in build_composite_combiner()
9707 subop += "()"; in build_composite_combiner()
9719 if (!remove_duplicate_swizzle(subop)) in build_composite_combiner()
9720 remove_unity_swizzle(base, subop); in build_composite_combiner()
9723 strip_enclosed_expression(subop); in build_composite_combiner()
9725 op += subop; in build_composite_combiner()
9728 op += subop; in build_composite_combiner()
9735 subop = to_composite_constructor_expression(elems[i], uses_buffer_offset); in build_composite_combiner()
9744 subop += "()"; in build_composite_combiner()
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