| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_sdma_copy_image.c | 154 struct si_texture *tiled = ssrc->surface.is_linear ? sdst : ssrc; in si_sdma_v4_v5_copy_texture() local
155 struct si_texture *linear = tiled == ssrc ? sdst : ssrc; in si_sdma_v4_v5_copy_texture()
156 unsigned tiled_width = DIV_ROUND_UP(tiled->buffer.b.b.width0, tiled->surface.blk_w); in si_sdma_v4_v5_copy_texture()
157 unsigned tiled_height = DIV_ROUND_UP(tiled->buffer.b.b.height0, tiled->surface.blk_h); in si_sdma_v4_v5_copy_texture()
160 uint64_t tiled_address = tiled == ssrc ? src_address : dst_address; in si_sdma_v4_v5_copy_texture()
164 bool dcc = vi_dcc_enabled(tiled, 0) && is_v5; in si_sdma_v4_v5_copy_texture()
165 assert(tiled->buffer.b.b.depth0 == 1); in si_sdma_v4_v5_copy_texture()
181 (is_v5 ? 0 : tiled->buffer.b.b.last_level) << 20 | in si_sdma_v4_v5_copy_texture()
183 radeon_emit((uint32_t)tiled_address | (tiled->surface.tile_swizzle << 8)); in si_sdma_v4_v5_copy_texture()
189 tiled->surface.u.gfx9.swizzle_mode << 3 | in si_sdma_v4_v5_copy_texture()
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| /third_party/mesa3d/src/panfrost/shared/test/ |
| D | test-tiling.cpp | 140 void *tiled = calloc(bpp, tiled_width * tiled_height); in test() local
149 panfrost_store_tiled_image(tiled, linear, rx, ry, rw, rh, in test()
153 ((uint8_t *) tiled)[i] = (i & 0xFF); in test()
156 panfrost_load_tiled_image(linear, tiled, rx, ry, rw, rh, in test()
160 ref_access_tiled(ref, store ? linear : tiled, rx, ry, rw, rh, in test()
164 EXPECT_EQ(memcmp(ref, tiled, bpp * tiled_width * tiled_height), 0); in test()
169 free(tiled); in test()
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| /third_party/mesa3d/src/amd/vulkan/ |
| D | radv_formats.c | 696 VkFormatFeatureFlags2 linear = 0, tiled = 0, buffer = 0; in radv_physical_device_get_format_properties() local
703 out_properties->optimalTilingFeatures = tiled; in radv_physical_device_get_format_properties()
711 out_properties->optimalTilingFeatures = tiled; in radv_physical_device_get_format_properties()
741 tiled |= VK_FORMAT_FEATURE_2_STORAGE_IMAGE_BIT | in radv_physical_device_get_format_properties()
763 tiled |= VK_FORMAT_FEATURE_2_DEPTH_STENCIL_ATTACHMENT_BIT; in radv_physical_device_get_format_properties()
764 tiled |= VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_BIT; in radv_physical_device_get_format_properties()
765 tiled |= VK_FORMAT_FEATURE_2_BLIT_SRC_BIT | VK_FORMAT_FEATURE_2_BLIT_DST_BIT; in radv_physical_device_get_format_properties()
766 tiled |= VK_FORMAT_FEATURE_2_TRANSFER_SRC_BIT | VK_FORMAT_FEATURE_2_TRANSFER_DST_BIT; in radv_physical_device_get_format_properties()
769 tiled |= VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_FILTER_MINMAX_BIT; in radv_physical_device_get_format_properties()
772 tiled |= VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_FILTER_LINEAR_BIT | in radv_physical_device_get_format_properties()
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| /third_party/mesa3d/src/gallium/drivers/lima/ |
| D | lima_resource.c | 228 res->tiled = should_tile; in _lima_resource_create_with_modifiers()
330 res->tiled = false; in lima_resource_from_handle()
333 res->tiled = true; in lima_resource_from_handle()
339 res->tiled = false; in lima_resource_from_handle()
348 if (res->tiled || in lima_resource_from_handle()
357 if (res->tiled && res->levels[0].stride != stride) { in lima_resource_from_handle()
363 if (!res->tiled && (res->levels[0].stride % 8)) { in lima_resource_from_handle()
368 if (!res->tiled && res->levels[0].stride < stride) { in lima_resource_from_handle()
413 if (res->tiled) in lima_resource_get_handle()
449 if (res->tiled) in lima_resource_get_param()
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| D | lima_resource.h | 59 bool tiled; member
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| /third_party/mesa3d/src/gallium/drivers/vc4/ |
| D | vc4_resource.c | 181 if (rsc->tiled) { in vc4_resource_transfer_map()
235 if (!rsc->tiled || in vc4_texture_subdata()
276 if (rsc->tiled) in vc4_resource_modifier()
382 if (!rsc->tiled) { in vc4_setup_slices()
482 if (!rsc->tiled) { in get_resource_texture_format()
544 rsc->tiled = should_tile; in vc4_resource_create_with_modifiers()
548 rsc->tiled = true; in vc4_resource_create_with_modifiers()
550 rsc->tiled = false; in vc4_resource_create_with_modifiers()
565 if (rsc->tiled) in vc4_resource_create_with_modifiers()
661 rsc->tiled = false; in vc4_resource_from_handle()
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| D | vc4_resource.h | 58 bool tiled; member
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| /third_party/mesa3d/src/gallium/drivers/v3d/ |
| D | v3d_resource.c | 295 if (rsc->tiled) { in v3d_resource_transfer_map()
355 if (!rsc->tiled) { in v3d_texture_subdata()
403 if (rsc->tiled) { in v3d_resource_modifier()
587 if (!rsc->tiled) { in v3d_setup_slices()
804 rsc->tiled = should_tile; in v3d_resource_create_with_modifiers()
808 rsc->tiled = true; in v3d_resource_create_with_modifiers()
810 rsc->tiled = false; in v3d_resource_create_with_modifiers()
885 rsc->tiled = false; in v3d_resource_from_handle()
888 rsc->tiled = true; in v3d_resource_from_handle()
891 rsc->tiled = screen->ro == NULL; in v3d_resource_from_handle()
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| D | v3d_blit.c | 77 struct pipe_resource *tiled = NULL; in v3d_render_blit() local
82 if (!src->tiled && in v3d_render_blit()
102 tiled = ctx->screen->resource_create(ctx->screen, &tmpl); in v3d_render_blit()
103 if (!tiled) { in v3d_render_blit()
108 tiled, 0, in v3d_render_blit()
113 info->src.resource = tiled; in v3d_render_blit()
126 pipe_resource_reference(&tiled, NULL); in v3d_render_blit()
758 if (src->tiled) in v3d_sand8_blit()
767 assert(dst->tiled); in v3d_sand8_blit()
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| D | v3d_resource.h | 96 bool tiled; member
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| /third_party/mesa3d/docs/isl/ |
| D | tiling.rst | 20 The basic idea of a tiled image is that the image is first divided into
23 demonstrated with a specific example. Suppose we have a RGBA8888 X-tiled
32 :alt: Example of an X-tiled image
35 instead, Y-tiled. Then the surface is divided into 32x32 pixel tiles each of
123 simply said it was Y-tiled but by Sky Lake there is almost no mention of
124 Y-tiling in connection with stencil buffers and they are always W-tiled. This
162 tiled address:
199 Starting with Sky Lake, we can scan out from Y-tiled buffers.
204 When bit-6 swizzling is enabled, bit 9 is XOR'd in with bit 6 of the tiled
232 the docs are somewhat confused as to whether stencil buffers are W or Y-tiled.
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| D | ccs.rst | 44 on the main surface of 16x16 sets of 128 byte Y-tiled cache-line-pairs.
45 CCS is always Y tiled.
58 two cache lines being vertically adjacent when the main surface is X-tiled and
59 horizontally adjacent when the main surface is Y-tiled. For an X-tiled surface
60 this forms an area of 64B x 2rows and for a Y-tiled surface this forms an area
133 boundary: horizontal when the primary surface is X-tiled and vertical when
134 Y-tiled. For a 32bpp format, this works out to an alignment of 256x128 main
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| /third_party/mesa3d/src/asahi/lib/ |
| D | tiling.h | 29 void agx_detile(void *tiled, void *linear,
33 void agx_tile(void *tiled, void *linear,
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| D | tiling.c | 98 pixel_t *tiled = _tiled; \
112 pixel_t *ptiled = &tiled[tile_base + y_offs + x_offs];\
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| /third_party/ffmpeg/tests/ref/fate/ |
| D | matroska-spherical-mono-remux | 33 projection=tiled equirectangular
57 projection=tiled equirectangular
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| D | mov-spherical-mono | 9 projection=tiled equirectangular
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| D | matroska-spherical-mono | 9 projection=tiled equirectangular
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| /third_party/libdrm/omap/ |
| D | omap_drm.c | 212 bo->size = round_up(size.tiled.width, PAGE_SIZE) * size.tiled.height; in omap_bo_new_impl()
244 .tiled = { in omap_bo_new_tiled()
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| D | omap_drm.h | 72 } tiled; /* (for tiled formats) */ member
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| /third_party/openGLES/extensions/INTEL/ |
| D | INTEL_map_texture.txt | 41 textures are often 'tiled'. Texels are kept in specific layout to improve
108 implementation-specific format, including tiled formats, by calling
143 image are located at 'stride' bytes distance within each other. For tiled
164 tiled when accessed by the GPU, however in many scenarios direct access to
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| /third_party/skia/third_party/externals/opengl-registry/extensions/INTEL/ |
| D | INTEL_map_texture.txt | 41 textures are often 'tiled'. Texels are kept in specific layout to improve
108 implementation-specific format, including tiled formats, by calling
143 image are located at 'stride' bytes distance within each other. For tiled
164 tiled when accessed by the GPU, however in many scenarios direct access to
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| /third_party/mesa3d/docs/relnotes/ |
| D | 21.1.2.rst | 127 - i965: Don't advertise Y-tiled modifiers for scanout buffers on Gfx8-
128 - iris: Don't advertise Y-tiled modifiers for scanout buffers on Gfx8
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| /third_party/flutter/skia/src/gpu/gradients/ |
| D | README.md | 26 convert the tiled t value (guaranteed to be within 0 and 1) into an output
40 valid tiled t value is in sk_InColor.x and can safely ignore y, z, and w.
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| D | GrTiledGradientEffect.fp | 41 // t.x has been tiled (repeat or mirrored), but pass through remaining 3 components
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| /third_party/mesa3d/src/broadcom/vulkan/ |
| D | v3dv_image.c | 135 if (!image->tiled) { in v3d_setup_slices()
212 image->alignment = image->tiled ? 4096 : image->cpp; in v3d_setup_slices()
329 image->tiled = tiling == VK_IMAGE_TILING_OPTIMAL || in create_image()
|