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Searched refs:tiling_flags (Results 1 – 18 of 18) sorted by relevance

/third_party/mesa3d/src/amd/vulkan/winsys/amdgpu/
Dradv_amdgpu_bo.c890 uint64_t tiling_flags = 0; in radv_amdgpu_winsys_bo_set_metadata() local
893 tiling_flags |= AMDGPU_TILING_SET(SWIZZLE_MODE, md->u.gfx9.swizzle_mode); in radv_amdgpu_winsys_bo_set_metadata()
894 tiling_flags |= AMDGPU_TILING_SET(DCC_OFFSET_256B, md->u.gfx9.dcc_offset_256b); in radv_amdgpu_winsys_bo_set_metadata()
895 tiling_flags |= AMDGPU_TILING_SET(DCC_PITCH_MAX, md->u.gfx9.dcc_pitch_max); in radv_amdgpu_winsys_bo_set_metadata()
896 tiling_flags |= AMDGPU_TILING_SET(DCC_INDEPENDENT_64B, md->u.gfx9.dcc_independent_64b_blocks); in radv_amdgpu_winsys_bo_set_metadata()
897 tiling_flags |= in radv_amdgpu_winsys_bo_set_metadata()
899 tiling_flags |= in radv_amdgpu_winsys_bo_set_metadata()
901 tiling_flags |= AMDGPU_TILING_SET(SCANOUT, md->u.gfx9.scanout); in radv_amdgpu_winsys_bo_set_metadata()
904 tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 4); /* 2D_TILED_THIN1 */ in radv_amdgpu_winsys_bo_set_metadata()
906 tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 2); /* 1D_TILED_THIN1 */ in radv_amdgpu_winsys_bo_set_metadata()
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/third_party/mesa3d/src/gallium/winsys/radeon/drm/
Dradeon_drm_bo.c893 if (args.tiling_flags & RADEON_TILING_MACRO) in radeon_bo_get_metadata()
895 else if (args.tiling_flags & RADEON_TILING_MICRO) in radeon_bo_get_metadata()
900 …surf->u.legacy.bankw = (args.tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANK… in radeon_bo_get_metadata()
901 …surf->u.legacy.bankh = (args.tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANK… in radeon_bo_get_metadata()
902 …surf->u.legacy.tile_split = (args.tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILI… in radeon_bo_get_metadata()
904 …surf->u.legacy.mtilea = (args.tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_T… in radeon_bo_get_metadata()
906 if (bo->rws->gen >= DRV_SI && !(args.tiling_flags & RADEON_TILING_R600_NO_SCANOUT)) in radeon_bo_get_metadata()
915 if (args.tiling_flags & RADEON_TILING_MICRO) in radeon_bo_get_metadata()
917 else if (args.tiling_flags & RADEON_TILING_MICRO_SQUARE) in radeon_bo_get_metadata()
920 if (args.tiling_flags & RADEON_TILING_MACRO) in radeon_bo_get_metadata()
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/third_party/libdrm/radeon/
Dradeon_bo.c98 uint32_t tiling_flags, uint32_t pitch) in radeon_bo_set_tiling() argument
101 return boi->bom->funcs->bo_set_tiling(boi, tiling_flags, pitch); in radeon_bo_set_tiling()
106 uint32_t *tiling_flags, uint32_t *pitch) in radeon_bo_get_tiling() argument
109 return boi->bom->funcs->bo_get_tiling(boi, tiling_flags, pitch); in radeon_bo_get_tiling()
Dradeon_bo_gem.c227 static int bo_set_tiling(struct radeon_bo_int *boi, uint32_t tiling_flags, in bo_set_tiling() argument
234 args.tiling_flags = tiling_flags; in bo_set_tiling()
244 static int bo_get_tiling(struct radeon_bo_int *boi, uint32_t *tiling_flags, in bo_get_tiling() argument
260 *tiling_flags = args.tiling_flags; in bo_get_tiling()
Dradeon_bo_int.h37 int (*bo_set_tiling)(struct radeon_bo_int *bo, uint32_t tiling_flags,
39 int (*bo_get_tiling)(struct radeon_bo_int *bo, uint32_t *tiling_flags,
Dradeon_bo.h67 int radeon_bo_set_tiling(struct radeon_bo *bo, uint32_t tiling_flags, uint32_t pitch);
68 int radeon_bo_get_tiling(struct radeon_bo *bo, uint32_t *tiling_flags, uint32_t *pitch);
/third_party/mesa3d/src/amd/common/
Dac_surface.c2620 uint64_t tiling_flags, enum radeon_surf_mode *mode) in ac_surface_set_bo_metadata() argument
2625 surf->u.gfx9.swizzle_mode = AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE); in ac_surface_set_bo_metadata()
2627 AMDGPU_TILING_GET(tiling_flags, DCC_INDEPENDENT_64B); in ac_surface_set_bo_metadata()
2629 AMDGPU_TILING_GET(tiling_flags, DCC_INDEPENDENT_128B); in ac_surface_set_bo_metadata()
2631 AMDGPU_TILING_GET(tiling_flags, DCC_MAX_COMPRESSED_BLOCK_SIZE); in ac_surface_set_bo_metadata()
2632 surf->u.gfx9.color.display_dcc_pitch_max = AMDGPU_TILING_GET(tiling_flags, DCC_PITCH_MAX); in ac_surface_set_bo_metadata()
2633 scanout = AMDGPU_TILING_GET(tiling_flags, SCANOUT); in ac_surface_set_bo_metadata()
2637 surf->u.legacy.pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in ac_surface_set_bo_metadata()
2638 surf->u.legacy.bankw = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in ac_surface_set_bo_metadata()
2639 surf->u.legacy.bankh = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in ac_surface_set_bo_metadata()
[all …]
Dac_surface.h428 uint64_t tiling_flags, enum radeon_surf_mode *mode);
430 uint64_t *tiling_flags);
/third_party/mesa3d/src/intel/isl/tests/
Disl_surf_get_image_offset_test.c145 .tiling_flags = ISL_TILING_Y0_BIT); in test_bdw_2d_r8g8b8a8_unorm_512x512_array01_samples01_noaux_tiley0()
193 .tiling_flags = ISL_TILING_Y0_BIT); in test_bdw_2d_r8g8b8a8_unorm_1024x1024_array06_samples01_noaux_tiley0()
254 .tiling_flags = ISL_TILING_Y0_BIT); in test_bdw_3d_r8g8b8a8_unorm_256x256x256_levels09_tiley0()
/third_party/mesa3d/src/intel/isl/
Disl.c621 isl_tiling_flags_t tiling_flags = info->tiling_flags; in isl_surf_choose_tiling() local
626 assert(tiling_flags == ISL_TILING_HIZ_BIT); in isl_surf_choose_tiling()
627 *tiling = isl_tiling_flag_to_enum(tiling_flags); in isl_surf_choose_tiling()
635 tiling_flags == ISL_TILING_CCS_BIT; in isl_surf_choose_tiling()
637 tiling_flags == ISL_TILING_GFX12_CCS_BIT; in isl_surf_choose_tiling()
639 *tiling = isl_tiling_flag_to_enum(tiling_flags); in isl_surf_choose_tiling()
644 isl_gfx125_filter_tiling(dev, info, &tiling_flags); in isl_surf_choose_tiling()
646 isl_gfx6_filter_tiling(dev, info, &tiling_flags); in isl_surf_choose_tiling()
648 isl_gfx4_filter_tiling(dev, info, &tiling_flags); in isl_surf_choose_tiling()
653 if (tiling_flags & (1u << (__tiling))) { \ in isl_surf_choose_tiling()
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Disl.h1459 isl_tiling_flags_t tiling_flags; member
/third_party/mesa3d/src/gallium/drivers/crocus/
Dcrocus_resource.c181 isl_tiling_flags_t tiling_flags = ISL_TILING_ANY_MASK; in crocus_resource_configure_main() local
185 tiling_flags &= ~ISL_TILING_Y0_BIT; in crocus_resource_configure_main()
190 tiling_flags = 1 << res->mod_info->tiling; in crocus_resource_configure_main()
195 tiling_flags = 1 << res->mod_info->tiling; in crocus_resource_configure_main()
200 tiling_flags = ISL_TILING_LINEAR_BIT; in crocus_resource_configure_main()
202 tiling_flags = screen->devinfo.has_tiling_uapi ? in crocus_resource_configure_main()
225 tiling_flags = ISL_TILING_W_BIT; in crocus_resource_configure_main()
251 .tiling_flags = tiling_flags in crocus_resource_configure_main()
/third_party/mesa3d/src/gallium/drivers/iris/
Diris_resource.c667 isl_tiling_flags_t tiling_flags = 0; in iris_resource_configure_main() local
670 tiling_flags = 1 << res->mod_info->tiling; in iris_resource_configure_main()
673 tiling_flags = ISL_TILING_LINEAR_BIT; in iris_resource_configure_main()
676 tiling_flags = ISL_TILING_LINEAR_BIT; in iris_resource_configure_main()
678 tiling_flags = ISL_TILING_X_BIT; in iris_resource_configure_main()
680 tiling_flags = ISL_TILING_ANY_MASK; in iris_resource_configure_main()
733 .tiling_flags = tiling_flags in iris_resource_configure_main()
/third_party/libdrm/include/drm/
Dradeon_drm.h859 __u32 tiling_flags; member
865 __u32 tiling_flags; member
/third_party/mesa3d/src/intel/vulkan/
Danv_image.c908 .tiling_flags = ISL_TILING_ANY_MASK); in add_shadow_surface()
951 .tiling_flags = isl_tiling_flags); in add_primary_surface()
Danv_blorp.c183 .tiling_flags = ISL_TILING_LINEAR_BIT); in get_blorp_surf_for_anv_buffer()
/third_party/mesa3d/src/intel/blorp/
Dblorp_clear.c1536 .tiling_flags = ISL_TILING_Y0_BIT); in blorp_ccs_ambiguate()
Dblorp_blit.c3092 .tiling_flags = ISL_TILING_LINEAR_BIT); in do_buffer_copy()