Searched refs:tmu (Results 1 – 12 of 12) sorted by relevance
| /third_party/mesa3d/src/gallium/drivers/vc4/kernel/ |
| D | vc4_validate_shaders.c | 153 int tmu) in record_texture_sample() argument
166 &validation_state->tmu_setup[tmu], in record_texture_sample()
173 validation_state->tmu_setup[tmu].p_offset[i] = ~0; in record_texture_sample()
189 int tmu = waddr > QPU_W_TMU0_B; in check_tmu_write() local
191 bool is_direct = submit && validation_state->tmu_write_count[tmu] == 0; in check_tmu_write()
232 validation_state->tmu_setup[tmu].p_offset[1] = in check_tmu_write()
241 validation_state->tmu_setup[tmu].is_direct = true; in check_tmu_write()
251 if (validation_state->tmu_write_count[tmu] >= 4) { in check_tmu_write()
253 tmu); in check_tmu_write()
256 validation_state->tmu_setup[tmu].p_offset[validation_state->tmu_write_count[tmu]] = in check_tmu_write()
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| /third_party/mesa3d/src/broadcom/compiler/ |
| D | v3d33_tex.c | 183 struct qinst *tmu = vir_MOV_dest(c, dst, coords[i]); in v3d33_vir_emit_tex() local
186 tmu->uniform = texture_u[i]; in v3d33_vir_emit_tex()
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| D | nir_to_vir.c | 263 if (c->tmu.flush_count >= MAX_TMU_QUEUE_SIZE) in ntq_tmu_fifo_overflow()
267 c->tmu.output_fifo_size + components > 16 / c->threads; in ntq_tmu_fifo_overflow()
277 if (c->tmu.flush_count == 0) in ntq_flush_tmu()
283 for (int i = 0; i < c->tmu.flush_count; i++) { in ntq_flush_tmu()
284 if (c->tmu.flush[i].component_mask > 0) { in ntq_flush_tmu()
285 nir_dest *dest = c->tmu.flush[i].dest; in ntq_flush_tmu()
289 if (c->tmu.flush[i].component_mask & (1 << j)) { in ntq_flush_tmu()
300 c->tmu.output_fifo_size = 0; in ntq_flush_tmu()
301 c->tmu.flush_count = 0; in ntq_flush_tmu()
302 _mesa_set_clear(c->tmu.outstanding_regs, NULL); in ntq_flush_tmu()
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| D | v3d_compiler.h | 648 } tmu; member
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| D | vir.c | 595 c->tmu.outstanding_regs = _mesa_pointer_set_create(c); in vir_compile_init()
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| /third_party/mesa3d/src/gallium/drivers/vc4/ |
| D | vc4_program.c | 463 struct qinst *tmu; in ntq_emit_tex() local
465 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_R, 0), r); in ntq_emit_tex()
466 tmu->src[qir_get_tex_uniform_src(tmu)] = in ntq_emit_tex()
472 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_R, 0), in ntq_emit_tex()
475 tmu->src[qir_get_tex_uniform_src(tmu)] = in ntq_emit_tex()
487 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_T, 0), t); in ntq_emit_tex()
488 tmu->src[qir_get_tex_uniform_src(tmu)] = in ntq_emit_tex()
492 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_B, 0), lod); in ntq_emit_tex()
493 tmu->src[qir_get_tex_uniform_src(tmu)] = in ntq_emit_tex()
497 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_S, 0), s); in ntq_emit_tex()
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| /third_party/mesa3d/src/gallium/drivers/r300/compiler/ |
| D | radeon_program_tex.c | 36 int tmu) in shadow_fail_value() argument
42 compiler->state.unit[tmu].texture_swizzle); in shadow_fail_value()
47 int tmu) in shadow_pass_value() argument
53 compiler->state.unit[tmu].texture_swizzle); in shadow_pass_value()
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| /third_party/gstreamer/gstplugins_bad/ext/resindvd/ |
| D | resindvdsrc.c | 2754 if (title_tmap->tmu == 0) in rsn_dvdsrc_get_sector_from_time_tmap()
2757 entry = ts / (title_tmap->tmu * GST_SECOND); in rsn_dvdsrc_get_sector_from_time_tmap()
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| /third_party/mesa3d/docs/relnotes/ |
| D | 22.1.0.rst | 1450 - broadcom/compiler: define max number of tmu spills for compile strategies
1463 - broadcom/compiler: disallow TMU spills if max tmu spills is 0
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| D | 20.1.0.rst | 273 - v3d/tex: don't configure tmu config 1 if not needed
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| D | 21.1.0.rst | 2345 - broadcom/compiler: fix end of tmu sequence detection
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| /third_party/openh264/res/ |
| D | Cisco_Absolute_Power_1280x720_30fps.yuv | 3097 …0-,+,)*.0-10-'()'+,+.//156502012-+23/023002//0014.,//./.../-,./,+&3_{���}tmu�~f`jn���~ehlhjqsnpu…
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