| /third_party/libunwind/tests/ |
| D | Gia64-test-rbs.c | 71 #define SPL(n) rbs_spill_##n macro
74 SPL(2), SPL(3), SPL(4), SPL(5), SPL(6), SPL(7),
75 SPL(8), SPL(9), SPL(10), SPL(11), SPL(12), SPL(13), SPL(14), SPL(15),
76 SPL(16), SPL(17), SPL(18), SPL(19), SPL(20), SPL(21), SPL(22), SPL(23),
77 SPL(24), SPL(25), SPL(26), SPL(27), SPL(28), SPL(29), SPL(30), SPL(31),
78 SPL(32), SPL(33), SPL(34), SPL(35), SPL(36), SPL(37), SPL(38), SPL(39),
79 SPL(40), SPL(41), SPL(42), SPL(43), SPL(44), SPL(45), SPL(46), SPL(47),
80 SPL(48), SPL(49), SPL(50), SPL(51), SPL(52), SPL(53), SPL(54), SPL(55),
81 SPL(56), SPL(57), SPL(58), SPL(59), SPL(60), SPL(61), SPL(62), SPL(63),
82 SPL(64), SPL(65), SPL(66), SPL(67), SPL(68), SPL(69), SPL(70), SPL(71),
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCTargetDesc.cpp | 155 {codeview::RegisterId::SPL, X86::SPL}, in initLLVMToSEHAndCVRegMapping()
613 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegisterOrZero()
641 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegisterOrZero()
642 return X86::SPL; in getX86SubSuperRegisterOrZero()
678 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegisterOrZero()
714 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegisterOrZero()
750 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegisterOrZero()
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| D | X86BaseInfo.h | 1131 return (reg == X86::SPL || reg == X86::BPL || in isX86_64NonExtLowByteReg()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.td | 76 def SPL : AVRReg<32, "SPL">, DwarfRegNum<[32]>;
83 def SP : AVRReg<32, "SP", [SPL, SPH]>, DwarfRegNum<[32]>;
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| D | AVRRegisterInfo.cpp | 62 Reserved.set(AVR::SPL); in getReservedRegs()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/ |
| D | NVPTXRegisterInfo.td | 26 def VRFrameLocal : NVPTXReg<"%SPL">;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.cpp | 582 Reserved.set(X86::SPL); in getReservedRegs()
606 {X86::SIL, X86::DIL, X86::BPL, X86::SPL, in getReservedRegs()
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| D | X86RegisterInfo.td | 68 def SPL : X86Reg<"spl", 4>;
124 def SP : X86Reg<"sp", 4, [SPL,SPH]>;
380 // In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and
390 (add AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.h | 95 ENTRY(SPL) \
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/IPO/ |
| D | SampleProfile.cpp | 182 SampleCoverageTracker(SampleProfileLoader &SPL) : SPLoader(SPL){}; in SampleCoverageTracker() argument
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/DebugInfo/CodeView/ |
| D | CodeViewRegisters.def | 217 CV_REGISTER(SPL, 327)
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/ |
| D | X86GenRegisterInfo.inc | 84 SPL = 64,
1176 { X86::SPL },
1316 …AH, X86::CH, X86::DH, X86::BL, X86::BH, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B…
6259 …= { X86::AL, X86::CL, X86::DL, X86::BL, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B…
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| D | X86GenAsmMatcher.inc | 7101 case X86::SPL: OpKind = MCK_GR8; break;
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| /third_party/ffmpeg/doc/ |
| D | encoders.texi | 235 Mixing Level. Specifies peak sound pressure level (SPL) in the production
|