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Searched refs:SrcOp (Results 1 – 25 of 35) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DMachineIRBuilder.h120 class SrcOp {
130 SrcOp(Register R) : Reg(R), Ty(SrcType::Ty_Reg) {} in SrcOp() function
131 SrcOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(SrcType::Ty_Reg) {} in SrcOp() function
132 SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {} in SrcOp() function
133 SrcOp(const CmpInst::Predicate P) : Pred(P), Ty(SrcType::Ty_Predicate) {} in SrcOp() function
137 SrcOp(unsigned) = delete;
138 SrcOp(int) = delete;
139 SrcOp(uint64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {} in SrcOp() function
140 SrcOp(int64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {} in SrcOp() function
381 MachineInstrBuilder buildDynStackAlloc(const DstOp &Res, const SrcOp &Size,
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DConstantFoldingMIRBuilder.h29 ArrayRef<SrcOp> SrcOps,
50 const SrcOp &Src0 = SrcOps[0];
51 const SrcOp &Src1 = SrcOps[1];
61 const SrcOp &Src0 = SrcOps[0];
62 const SrcOp &Src1 = SrcOps[1];
DCSEMIRBuilder.h63 void profileSrcOp(const SrcOp &Op, GISelInstProfileBuilder &B) const;
65 void profileSrcOps(ArrayRef<SrcOp> Ops, GISelInstProfileBuilder &B) const { in profileSrcOps()
66 for (const SrcOp &Op : Ops) in profileSrcOps()
73 ArrayRef<SrcOp> SrcOps, Optional<unsigned> Flags,
95 ArrayRef<SrcOp> SrcOps,
DLegalizationArtifactCombiner.h300 unsigned SrcOp = SrcDef->getOpcode(); in tryCombineMerges() local
301 if (isArtifactCast(SrcOp)) { in tryCombineMerges()
302 ConvertOp = SrcOp; in tryCombineMerges()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DMachineIRBuilder.cpp164 const SrcOp &Size, in buildDynStackAlloc()
215 const SrcOp &Op0, in buildPtrAdd()
216 const SrcOp &Op1) { in buildPtrAdd()
241 const SrcOp &Op0, in buildPtrMask()
274 const SrcOp &Op) { in buildCopy()
361 const SrcOp &Addr, in buildLoad()
368 const SrcOp &Addr, in buildLoadInstr()
380 MachineInstrBuilder MachineIRBuilder::buildStore(const SrcOp &Val, in buildStore()
381 const SrcOp &Addr, in buildStore()
395 const SrcOp &Op0, in buildUAddo()
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DCSEMIRBuilder.cpp70 void CSEMIRBuilder::profileSrcOp(const SrcOp &Op, in profileSrcOp()
73 case SrcOp::SrcType::Ty_Predicate: in profileSrcOp()
91 ArrayRef<SrcOp> SrcOps, in profileEverything()
139 ArrayRef<SrcOp> SrcOps, in buildInstr()
169 const SrcOp &Src0 = SrcOps[0]; in buildInstr()
170 const SrcOp &Src1 = SrcOps[1]; in buildInstr()
DLegalizerHelper.cpp1351 SrcOp Src(SrcReg); in widenScalarExtract()
2380 SmallVector<SrcOp, 4> SrcOps; in fewerElementsVectorBasic()
2396 SmallVector<SrcOp, 4> SrcOps; in fewerElementsVectorBasic()
3102 SrcOp Lo(Register(0)), Hi(Register(0)); in narrowScalarShiftByConstant()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Linker/
DIRMover.cpp1227 MDNode *SrcOp = SrcModFlags->getOperand(I); in linkModuleFlagsMetadata() local
1229 mdconst::extract<ConstantInt>(SrcOp->getOperand(0)); in linkModuleFlagsMetadata()
1230 MDString *ID = cast<MDString>(SrcOp->getOperand(1)); in linkModuleFlagsMetadata()
1240 if (Requirements.insert(cast<MDNode>(SrcOp->getOperand(2)))) { in linkModuleFlagsMetadata()
1241 DstModFlags->addOperand(SrcOp); in linkModuleFlagsMetadata()
1248 Flags[ID] = std::make_pair(SrcOp, DstModFlags->getNumOperands()); in linkModuleFlagsMetadata()
1249 DstModFlags->addOperand(SrcOp); in linkModuleFlagsMetadata()
1259 DstModFlags->setOperand(DstIndex, SrcOp); in linkModuleFlagsMetadata()
1260 Flags[ID].first = SrcOp; in linkModuleFlagsMetadata()
1267 SrcOp->getOperand(2) != DstOp->getOperand(2)) in linkModuleFlagsMetadata()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSILowerControlFlow.cpp465 for (const auto &SrcOp : Def->explicit_operands()) in findMaskOperands() local
466 if (SrcOp.isReg() && SrcOp.isUse() && in findMaskOperands()
467 (Register::isVirtualRegister(SrcOp.getReg()) || SrcOp.getReg() == Exec)) in findMaskOperands()
468 Src.push_back(SrcOp); in findMaskOperands()
DSIPeepholeSDWA.cpp163 const MachineOperand *SrcOp) const;
331 const MachineOperand *SrcOp) const { in getSrcMods()
333 const auto *MI = SrcOp->getParent(); in getSrcMods()
334 if (TII->getNamedOperand(*MI, AMDGPU::OpName::src0) == SrcOp) { in getSrcMods()
338 } else if (TII->getNamedOperand(*MI, AMDGPU::OpName::src1) == SrcOp) { in getSrcMods()
DSIInstrInfo.cpp1432 const MachineOperand &SrcOp = MI.getOperand(1); in expandPostRAPseudo() local
1434 assert(!SrcOp.isFPImm()); in expandPostRAPseudo()
1435 if (SrcOp.isImm()) { in expandPostRAPseudo()
1436 APInt Imm(64, SrcOp.getImm()); in expandPostRAPseudo()
1444 assert(SrcOp.isReg()); in expandPostRAPseudo()
1446 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0)) in expandPostRAPseudo()
1449 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1)) in expandPostRAPseudo()
1596 const MachineOperand &SrcOp = MI.getOperand(I); in expandMovDPP64() local
1597 assert(!SrcOp.isFPImm()); in expandMovDPP64()
1598 if (SrcOp.isImm()) { in expandMovDPP64()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonExpandCondsets.cpp213 MachineInstr *genCondTfrFor(MachineOperand &SrcOp,
623 MachineInstr *HexagonExpandCondsets::genCondTfrFor(MachineOperand &SrcOp, in genCondTfrFor() argument
627 MachineInstr *MI = SrcOp.getParent(); in genCondTfrFor()
637 unsigned Opc = getCondTfrOpcode(SrcOp, PredSense); in genCondTfrFor()
642 if (SrcOp.isReg()) { in genCondTfrFor()
643 unsigned SrcState = getRegState(SrcOp); in genCondTfrFor()
644 if (RegisterRef(SrcOp) == RegisterRef(DstR, DstSR)) in genCondTfrFor()
649 .addReg(SrcOp.getReg(), SrcState, SrcOp.getSubReg()); in genCondTfrFor()
654 .add(SrcOp); in genCondTfrFor()
DHexagonRDFOpt.cpp139 const MachineOperand &SrcOp = MI->getOperand(1); in INITIALIZE_PASS_DEPENDENCY() local
141 DFG.makeRegRef(SrcOp.getReg(), SrcOp.getSubReg())); in INITIALIZE_PASS_DEPENDENCY()
DHexagonFrameLowering.cpp2305 MachineOperand &SrcOp = SI.getOperand(2); in optimizeSpillSlots() local
2307 HexagonBlockRanges::RegisterRef SrcRR = { SrcOp.getReg(), in optimizeSpillSlots()
2308 SrcOp.getSubReg() }; in optimizeSpillSlots()
2330 .add(SrcOp); in optimizeSpillSlots()
2337 if (unsigned SR = SrcOp.getSubReg()) in optimizeSpillSlots()
2338 SrcOp.setReg(HRI.getSubReg(FoundR, SR)); in optimizeSpillSlots()
2340 SrcOp.setReg(FoundR); in optimizeSpillSlots()
2341 SrcOp.setSubReg(0); in optimizeSpillSlots()
2343 SrcOp.setIsKill(false); in optimizeSpillSlots()
DHexagonInstrInfo.cpp1098 const MachineOperand &SrcOp = MI.getOperand(2); in expandPostRAPseudo() local
1099 assert(SrcOp.getSubReg() == 0); in expandPostRAPseudo()
1109 .addReg(SrcOp.getReg(), getRegState(SrcOp)) in expandPostRAPseudo()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DMachineVerifier.cpp1279 const MachineOperand &SrcOp = MI->getOperand(1); in verifyPreISelGenericInstruction() local
1280 if (!SrcOp.isReg()) { in verifyPreISelGenericInstruction()
1292 unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits(); in verifyPreISelGenericInstruction()
1301 const MachineOperand &SrcOp = MI->getOperand(2); in verifyPreISelGenericInstruction() local
1302 if (!SrcOp.isReg()) { in verifyPreISelGenericInstruction()
1314 unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits(); in verifyPreISelGenericInstruction()
1529 const MachineOperand &SrcOp = MI->getOperand(1); in visitMachineInstrBefore() local
1531 LLT SrcTy = MRI->getType(SrcOp.getReg()); in visitMachineInstrBefore()
1542 unsigned SrcSize = TRI->getRegSizeInBits(SrcOp.getReg(), *MRI); in visitMachineInstrBefore()
1547 if (!DstOp.getSubReg() && !SrcOp.getSubReg()) { in visitMachineInstrBefore()
DMachineScheduler.cpp1689 const MachineOperand &SrcOp = Copy->getOperand(1); in constrainLocalCopy() local
1690 Register SrcReg = SrcOp.getReg(); in constrainLocalCopy()
1691 if (!Register::isVirtualRegister(SrcReg) || !SrcOp.readsReg()) in constrainLocalCopy()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/InstCombine/
DInstructionCombining.cpp2196 Value *SrcOp = BCI->getOperand(0); in visitGetElementPtrInst() local
2222 ? Builder.CreateInBoundsGEP(SrcEltType, SrcOp, {Ops[1], Ops[2]}) in visitGetElementPtrInst()
2223 : Builder.CreateGEP(SrcEltType, SrcOp, {Ops[1], Ops[2]}); in visitGetElementPtrInst()
2240 if (!isa<BitCastInst>(SrcOp) && GEP.accumulateConstantOffset(DL, Offset)) { in visitGetElementPtrInst()
2246 if (isa<AllocaInst>(SrcOp) || isAllocationFn(SrcOp, &TLI)) { in visitGetElementPtrInst()
2259 return new AddrSpaceCastInst(SrcOp, GEPType); in visitGetElementPtrInst()
2260 return new BitCastInst(SrcOp, GEPType); in visitGetElementPtrInst()
2270 ? Builder.CreateInBoundsGEP(SrcEltType, SrcOp, NewIndices) in visitGetElementPtrInst()
2271 : Builder.CreateGEP(SrcEltType, SrcOp, NewIndices); in visitGetElementPtrInst()
DInstCombineCasts.cpp1118 if (auto *SrcOp = dyn_cast<Instruction>(Src)) in visitZExt() local
1119 if (SrcOp->hasOneUse()) in visitZExt()
1120 replaceAllDbgUsesWith(*SrcOp, *Res, CI, DT); in visitZExt()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Analysis/
DInstructionSimplify.cpp3287 Value *SrcOp = LI->getOperand(0); in SimplifyICmpInst() local
3288 Type *SrcTy = SrcOp->getType(); in SimplifyICmpInst()
3297 if (Value *V = SimplifyICmpInst(Pred, SrcOp, in SimplifyICmpInst()
3304 if (Value *V = SimplifyICmpInst(Pred, SrcOp, RI->getOperand(0), in SimplifyICmpInst()
3317 SrcOp, RI->getOperand(0), Q, in SimplifyICmpInst()
3333 SrcOp, Trunc, Q, MaxRecurse-1)) in SimplifyICmpInst()
3376 if (Value *V = SimplifyICmpInst(Pred, SrcOp, RI->getOperand(0), in SimplifyICmpInst()
3391 if (Value *V = SimplifyICmpInst(Pred, SrcOp, Trunc, Q, MaxRecurse-1)) in SimplifyICmpInst()
3423 if (Value *V = SimplifyICmpInst(ICmpInst::ICMP_SLT, SrcOp, in SimplifyICmpInst()
3432 if (Value *V = SimplifyICmpInst(ICmpInst::ICMP_SGE, SrcOp, in SimplifyICmpInst()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeDAG.cpp161 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT,
163 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT,
1745 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, EVT SlotVT, in EmitStackConvert() argument
1747 return EmitStackConvert(SrcOp, SlotVT, DestVT, dl, DAG.getEntryNode()); in EmitStackConvert()
1750 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, EVT SlotVT, in EmitStackConvert() argument
1755 SrcOp.getValueType().getTypeForEVT(*DAG.getContext())); in EmitStackConvert()
1763 unsigned SrcSize = SrcOp.getValueSizeInBits(); in EmitStackConvert()
1774 Store = DAG.getTruncStore(Chain, dl, SrcOp, FIPtr, PtrInfo, in EmitStackConvert()
1779 DAG.getStore(Chain, dl, SrcOp, FIPtr, PtrInfo, SrcAlign); in EmitStackConvert()
DSelectionDAG.cpp2543 SDValue SrcOp = Op.getOperand(i); in computeKnownBits() local
2544 Known2 = computeKnownBits(SrcOp, Depth + 1); in computeKnownBits()
2547 if (SrcOp.getValueSizeInBits() != BitWidth) { in computeKnownBits()
2548 assert(SrcOp.getValueSizeInBits() > BitWidth && in computeKnownBits()
3540 SDValue SrcOp = Op.getOperand(i); in ComputeNumSignBits() local
3544 if (SrcOp.getValueSizeInBits() != VTBits) { in ComputeNumSignBits()
3545 assert(SrcOp.getValueSizeInBits() > VTBits && in ComputeNumSignBits()
3547 unsigned ExtraBits = SrcOp.getValueSizeInBits() - VTBits; in ComputeNumSignBits()
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
DIceTargetLoweringX8664.cpp4487 Operand *SrcOp = VarAssign->getSrc(0); in matchAssign() local
4488 assert(SrcOp); in matchAssign()
4489 if (auto *SrcVar = llvm::dyn_cast<Variable>(SrcOp)) { in matchAssign()
4496 } else if (auto *Const = llvm::dyn_cast<ConstantInteger32>(SrcOp)) { in matchAssign()
4503 } else if (auto *AddReloc = llvm::dyn_cast<ConstantRelocatable>(SrcOp)) { in matchAssign()
DIceTargetLoweringX8632.cpp5066 Operand *SrcOp = VarAssign->getSrc(0); in matchAssign() local
5067 assert(SrcOp); in matchAssign()
5068 if (auto *SrcVar = llvm::dyn_cast<Variable>(SrcOp)) { in matchAssign()
5075 } else if (auto *Const = llvm::dyn_cast<ConstantInteger32>(SrcOp)) { in matchAssign()
5082 } else if (auto *AddReloc = llvm::dyn_cast<ConstantRelocatable>(SrcOp)) { in matchAssign()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86ISelLowering.cpp7925 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, unsigned NumBits, in getVShift() argument
7931 SrcOp = DAG.getBitcast(ShVT, SrcOp); in getVShift()
7934 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal)); in getVShift()
7937 static SDValue LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, const SDLoc &dl, in LowerAsSplatVectorLoad() argument
7943 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) { in LowerAsSplatVectorLoad()
23286 SDValue SrcOp, uint64_t ShiftAmt, in getTargetVShiftByConstNode() argument
23292 if (VT != SrcOp.getSimpleValueType()) in getTargetVShiftByConstNode()
23293 SrcOp = DAG.getBitcast(VT, SrcOp); in getTargetVShiftByConstNode()
23297 return SrcOp; in getTargetVShiftByConstNode()
23312 if (ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) { in getTargetVShiftByConstNode()
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