1 /* 2 * Copyright (c) 2021 Nanjing Xiaoxiongpai Intelligent Technology Co., Ltd. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef __TARGET_CONFIG_H__ 17 #define __TARGET_CONFIG_H__ 18 19 #ifdef __cplusplus 20 #if __cplusplus 21 extern "C" { 22 #endif /* __cplusplus */ 23 #endif /* __cplusplus */ 24 25 /* 26 MMU内存映射表 27 | DDR | DDR | PMM | PMM | PMM | GIC | ... | 28 | 256MB | 256MB | 512MB | 512MB | 512MB | 1M | xxx | 29 */ 30 31 #define OS_SYS_CLOCK (24000000) 32 #define SYS_CTRL_REG_BASE IO_DEVICE_ADDR(0x12020000) 33 #define REG_SC_CTRL 0 34 35 /* smp */ 36 #define CRG_REG_ADDR (0x12010000) 37 #define CRG_REG_BASE IO_DEVICE_ADDR(CRG_REG_ADDR) 38 #define PERI_CRG30_BASE IO_DEVICE_ADDR(CRG_REG_ADDR + 0x0078) /* cpu freq-mode & reset CRG */ 39 40 /* memory config */ 41 #define CACHE_ALIGNED_SIZE (64) 42 43 // 256MB 44 #ifdef LOSCFG_TEE_ENABLE 45 #define DDR_MEM_ADDR 0xC1000000 46 #define DDR_MEM_SIZE 0xf000000 47 #else 48 #define DDR_MEM_ADDR 0xBF000000 49 #define DDR_MEM_SIZE 0x11000000 50 #endif 51 52 #define SYS_MEM_BASE DDR_MEM_ADDR 53 #define SYS_MEM_SIZE_DEFAULT 0x07f00000 54 #define SYS_MEM_END (SYS_MEM_BASE + SYS_MEM_SIZE_DEFAULT) 55 56 /* Peripheral register address base and size */ 57 #define PERIPH_PMM_BASE 0x40000000 58 #define PERIPH_PMM_SIZE 0x20000000 59 60 /* kernel load address */ 61 #define KERNEL_LOAD_ADDRESS (0xC0100000) 62 63 /* hwi */ 64 /** 65 * 查手册获取中断号列表 66 * Maximum number of supported hardware devices that generate hardware interrupts. 67 * The maximum number of hardware devices that generate hardware interrupts is 288. 68 */ 69 #define OS_HWI_MAX_NUM 288 70 /** 71 * Maximum interrupt number. 72 */ 73 #define OS_HWI_MAX ((OS_HWI_MAX_NUM) - 1) 74 /** 75 * Minimum interrupt number. 76 */ 77 #define OS_HWI_MIN 0 78 /** 79 * Maximum usable interrupt number. 80 */ 81 #define OS_USER_HWI_MAX OS_HWI_MAX 82 /** 83 * Minimum usable interrupt number. 84 */ 85 #define OS_USER_HWI_MIN OS_HWI_MIN 86 87 /* 88 通用定时器中断号设置 89 使用 Non-secure 的时钟中断 90 */ 91 #define NUM_HAL_INTERRUPT_CNTPSIRQ 29 /* Secure physical timer event. */ 92 #define NUM_HAL_INTERRUPT_CNTPNSIRQ 30 /* Non-secure physical timer event. */ 93 #ifdef LOSCFG_TEE_ENABLE 94 #define OS_TICK_INT_NUM NUM_HAL_INTERRUPT_CNTPNSIRQ // use non-secure physical timer for now 95 #else 96 #define OS_TICK_INT_NUM NUM_HAL_INTERRUPT_CNTPSIRQ // use secure physical timer for now 97 #endif 98 99 #define NUM_HAL_INTERRUPT_TIMER0 37 100 #define NUM_HAL_INTERRUPT_TIMER3 38 101 #define NUM_HAL_INTERRUPT_UART4 84 102 103 /* GIC base and size : 1M-align */ 104 #define GIC_PHY_BASE 0xA0000000 105 #define GIC_PHY_SIZE 0x100000 106 107 /* GIC */ 108 #define GIC_VIRT_BASE (PERIPH_UNCACHED_BASE + PERIPH_UNCACHED_SIZE) 109 #define GIC_BASE_ADDR (GIC_VIRT_BASE + 0x20000) 110 #define GIC_VIRT_SIZE U32_C(GIC_PHY_SIZE) 111 #define GICD_OFFSET 0x1000 /* interrupt distributor offset */ 112 #define GICC_OFFSET 0x2000 /* CPU interface register offset */ 113 114 /* FB */ 115 #define FB_VIRT_BASE (GIC_VIRT_BASE + GIC_VIRT_SIZE) /* 虚拟地址放在GIC_VIRT后面 */ 116 #define FB_SIZE (0x400000 * 2) /* 4M * 2 */ 117 #define FB_PHY_BASE (DDR_MEM_ADDR + DDR_MEM_SIZE) /* 物理地址放在DDR后面 */ 118 119 #define BIT(n) (1U << (n)) 120 121 /* use UART4 as debug uart */ 122 #define UART4_REG_ADDR 0x40010000 123 #define UART4_REG_PBASE (UART4_REG_ADDR + 0x0000) 124 #define UART4_REG_BASE IO_DEVICE_ADDR(UART4_REG_PBASE) 125 #define TTY_DEVICE "/dev/uartdev-4" 126 #define UART_REG_BASE UART4_REG_BASE 127 #define DEBUG_UART_BASE UART4_REG_ADDR 128 #define NUM_HAL_INTERRUPT_UART NUM_HAL_INTERRUPT_UART4 129 130 #ifdef __cplusplus 131 #if __cplusplus 132 } 133 #endif /* __cplusplus */ 134 #endif /* __cplusplus */ 135 136 #endif 137