1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Rockchip USB3.0 and PCIE COMBPHY with Innosilicon IP block driver
4 *
5 * Copyright (C) 2018 Fuzhou Rockchip Electronics Co., Ltd.
6 */
7
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/io.h>
11 #include <linux/iopoll.h>
12 #include <linux/kernel.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/module.h>
15 #include <linux/of_device.h>
16 #include <linux/phy/phy.h>
17 #include <linux/phy/pcie.h>
18 #include <linux/regmap.h>
19 #include <linux/reset.h>
20 #include <dt-bindings/phy/phy.h>
21
22 #define BIT_WRITEABLE_SHIFT 16
23
24 struct rockchip_combphy_priv;
25
26 enum rockchip_combphy_rst {
27 OTG_RSTN = 0,
28 PHY_POR_RSTN = 1,
29 PHY_APB_RSTN = 2,
30 PHY_PIPE_RSTN = 3,
31 PHY_GRF_P_RSTN = 4,
32 PHY_RESET_MAX = 5,
33 };
34
35 struct combphy_reg {
36 u32 offset;
37 u32 bitend;
38 u32 bitstart;
39 u32 disable;
40 u32 enable;
41 };
42
43 struct rockchip_combphy_grfcfg {
44 struct combphy_reg pipe_l1_sel;
45 struct combphy_reg pipe_l1_set;
46 struct combphy_reg pipe_l1pd_sel;
47 struct combphy_reg pipe_l1pd_p3;
48 struct combphy_reg pipe_l0pd_sel;
49 struct combphy_reg pipe_l0pd_p3;
50 struct combphy_reg pipe_clk_sel;
51 struct combphy_reg pipe_clk_set;
52 struct combphy_reg pipe_rate_sel;
53 struct combphy_reg pipe_rate_set;
54 struct combphy_reg pipe_mode_sel;
55 struct combphy_reg pipe_mode_set;
56 struct combphy_reg pipe_txrx_sel;
57 struct combphy_reg pipe_txrx_set;
58 struct combphy_reg pipe_width_sel;
59 struct combphy_reg pipe_width_set;
60 struct combphy_reg pipe_usb3_sel;
61 struct combphy_reg pipe_pll_lock;
62 struct combphy_reg pipe_status_l0;
63 struct combphy_reg pipe_l0rxterm_sel;
64 struct combphy_reg pipe_l1rxterm_sel;
65 struct combphy_reg pipe_l0rxterm_set;
66 struct combphy_reg pipe_l1rxterm_set;
67 struct combphy_reg pipe_l0rxelec_set;
68 struct combphy_reg u3_port_disable;
69 struct combphy_reg u3_port_num;
70 };
71
72 struct rockchip_combphy_cfg {
73 const struct rockchip_combphy_grfcfg grfcfg;
74 int (*combphy_cfg)(struct rockchip_combphy_priv *priv);
75 int (*combphy_low_power_ctrl)(struct rockchip_combphy_priv *priv,
76 bool en);
77 };
78
79 struct rockchip_combphy_priv {
80 bool phy_initialized;
81 bool phy_suspended;
82 u8 phy_type;
83 void __iomem *mmio;
84 struct device *dev;
85 struct clk *ref_clk;
86 struct phy *phy;
87 struct regmap *combphy_grf;
88 struct regmap *usb_pcie_grf;
89 struct reset_control *rsts[PHY_RESET_MAX];
90 const struct rockchip_combphy_cfg *cfg;
91 };
92
get_reset_name(enum rockchip_combphy_rst rst)93 static const char *get_reset_name(enum rockchip_combphy_rst rst)
94 {
95 switch (rst) {
96 case OTG_RSTN:
97 return "otg-rst";
98 case PHY_POR_RSTN:
99 return "combphy-por";
100 case PHY_APB_RSTN:
101 return "combphy-apb";
102 case PHY_PIPE_RSTN:
103 return "combphy-pipe";
104 case PHY_GRF_P_RSTN:
105 return "usb3phy_grf_p";
106 default:
107 return "invalid";
108 }
109 }
110
param_read(struct regmap * base,const struct combphy_reg * reg,u32 val)111 static inline bool param_read(struct regmap *base,
112 const struct combphy_reg *reg, u32 val)
113 {
114 int ret;
115 u32 mask, orig, tmp;
116
117 ret = regmap_read(base, reg->offset, &orig);
118 if (ret)
119 return false;
120
121 mask = GENMASK(reg->bitend, reg->bitstart);
122 tmp = (orig & mask) >> reg->bitstart;
123
124 return tmp == val;
125 }
126
param_write(struct regmap * base,const struct combphy_reg * reg,bool en)127 static inline int param_write(struct regmap *base,
128 const struct combphy_reg *reg, bool en)
129 {
130 u32 val, mask, tmp;
131
132 tmp = en ? reg->enable : reg->disable;
133 mask = GENMASK(reg->bitend, reg->bitstart);
134 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
135
136 return regmap_write(base, reg->offset, val);
137 }
138
u3phy_mode_show(struct device * device,struct device_attribute * attr,char * buf)139 static ssize_t u3phy_mode_show(struct device *device,
140 struct device_attribute *attr,
141 char *buf)
142 {
143 struct rockchip_combphy_priv *priv = dev_get_drvdata(device);
144
145 if (param_read(priv->usb_pcie_grf, &priv->cfg->grfcfg.u3_port_num, 0))
146 return sprintf(buf, "u2\n");
147 else
148 return sprintf(buf, "u3\n");
149 }
150
u3phy_mode_store(struct device * device,struct device_attribute * attr,const char * buf,size_t count)151 static ssize_t u3phy_mode_store(struct device *device,
152 struct device_attribute *attr,
153 const char *buf, size_t count)
154 {
155 struct rockchip_combphy_priv *priv = dev_get_drvdata(device);
156
157 if (!strncmp(buf, "u3", 2) &&
158 param_read(priv->usb_pcie_grf, &priv->cfg->grfcfg.u3_port_num, 0)) {
159 /*
160 * Enable USB 3.0 rx termination, need to select
161 * pipe_l0_rxtermination from USB 3.0 controller.
162 */
163 param_write(priv->combphy_grf,
164 &priv->cfg->grfcfg.pipe_l0rxterm_sel, false);
165 /* Set xHCI USB 3.0 port number to 1 */
166 param_write(priv->usb_pcie_grf,
167 &priv->cfg->grfcfg.u3_port_num, true);
168 /* Enable xHCI USB 3.0 port */
169 param_write(priv->usb_pcie_grf,
170 &priv->cfg->grfcfg.u3_port_disable, false);
171 dev_info(priv->dev, "Set usb3.0 and usb2.0 mode successfully\n");
172 } else if (!strncmp(buf, "u2", 2) &&
173 param_read(priv->usb_pcie_grf,
174 &priv->cfg->grfcfg.u3_port_num, 1)) {
175 /*
176 * Disable USB 3.0 rx termination, need to select
177 * pipe_l0_rxtermination from grf and remove rx
178 * termimation by grf.
179 */
180 param_write(priv->combphy_grf,
181 &priv->cfg->grfcfg.pipe_l0rxterm_set, false);
182 param_write(priv->combphy_grf,
183 &priv->cfg->grfcfg.pipe_l0rxterm_sel, true);
184 /* Set xHCI USB 3.0 port number to 0 */
185 param_write(priv->usb_pcie_grf,
186 &priv->cfg->grfcfg.u3_port_num, false);
187 /* Disable xHCI USB 3.0 port */
188 param_write(priv->usb_pcie_grf,
189 &priv->cfg->grfcfg.u3_port_disable, true);
190 /*
191 * Note:
192 * Don't disable the USB 3.0 PIPE pclk here(set reg
193 * pipe_usb3_sel to false), because USB 3.0 PHY depend
194 * on this clk, if we disable it, we need to reinit
195 * the USB 3.0 PHY when use USB 3.0 mode, in order to
196 * simplify the process, don't disable this PIPE pclk.
197 */
198 dev_info(priv->dev, "Set usb2.0 only mode successfully\n");
199 } else {
200 dev_info(priv->dev, "Same or illegal mode\n");
201 }
202
203 return count;
204 }
205
206 static DEVICE_ATTR_RW(u3phy_mode);
207
208 static struct attribute *rockchip_combphy_u3phy_mode_attrs[] = {
209 &dev_attr_u3phy_mode.attr,
210 NULL,
211 };
212
213 static struct attribute_group rockchip_combphy_u3phy_mode_attr_group = {
214 .name = NULL, /* we want them in the same directory */
215 .attrs = rockchip_combphy_u3phy_mode_attrs,
216 };
217
rockchip_combphy_pll_lock(struct rockchip_combphy_priv * priv)218 static u32 rockchip_combphy_pll_lock(struct rockchip_combphy_priv *priv)
219 {
220 const struct rockchip_combphy_grfcfg *grfcfg;
221 u32 mask, val;
222
223 grfcfg = &priv->cfg->grfcfg;
224 mask = GENMASK(grfcfg->pipe_pll_lock.bitend,
225 grfcfg->pipe_pll_lock.bitstart);
226
227 regmap_read(priv->combphy_grf, grfcfg->pipe_pll_lock.offset, &val);
228 val = (val & mask) >> grfcfg->pipe_pll_lock.bitstart;
229
230 return val;
231 }
232
rockchip_combphy_is_ready(struct rockchip_combphy_priv * priv)233 static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv)
234 {
235 const struct rockchip_combphy_grfcfg *grfcfg;
236 u32 mask, val;
237
238 grfcfg = &priv->cfg->grfcfg;
239 mask = GENMASK(grfcfg->pipe_status_l0.bitend,
240 grfcfg->pipe_status_l0.bitstart);
241
242 regmap_read(priv->combphy_grf, grfcfg->pipe_status_l0.offset, &val);
243 val = (val & mask) >> grfcfg->pipe_status_l0.bitstart;
244
245 return val;
246 }
247
phy_pcie_init(struct rockchip_combphy_priv * priv)248 static int phy_pcie_init(struct rockchip_combphy_priv *priv)
249 {
250 const struct rockchip_combphy_grfcfg *grfcfg;
251 u32 val;
252 int ret = 0;
253
254 grfcfg = &priv->cfg->grfcfg;
255
256 /* reset PCIe phy to default configuration */
257 reset_control_assert(priv->rsts[PHY_POR_RSTN]);
258 reset_control_assert(priv->rsts[PHY_APB_RSTN]);
259 reset_control_assert(priv->rsts[PHY_PIPE_RSTN]);
260
261 reset_control_deassert(priv->rsts[PHY_POR_RSTN]);
262 /* Wait PHY power on stable */
263 udelay(5);
264 reset_control_deassert(priv->rsts[PHY_APB_RSTN]);
265 udelay(5);
266
267 /* Set rxtermination for lane0 */
268 param_write(priv->combphy_grf, &grfcfg->pipe_l0rxterm_set, true);
269 /* Set rxtermination for lane1 */
270 param_write(priv->combphy_grf, &grfcfg->pipe_l1rxterm_set, true);
271 /* Select pipe_l0_rxtermination from grf */
272 param_write(priv->combphy_grf, &grfcfg->pipe_l0rxterm_sel, true);
273 /* Select pipe_l1_rxtermination from grf */
274 param_write(priv->combphy_grf, &grfcfg->pipe_l1rxterm_sel, true);
275 /* Select rxelecidle_disable and txcommonmode from PCIe controller */
276 param_write(priv->combphy_grf, &grfcfg->pipe_txrx_sel, false);
277
278 /* Start to configurate PHY registers for PCIE. */
279 if (priv->cfg->combphy_cfg) {
280 ret = priv->cfg->combphy_cfg(priv);
281 if (ret)
282 goto error;
283 }
284
285 /* Wait Tx PLL lock */
286 usleep_range(300, 350);
287 ret = readx_poll_timeout_atomic(rockchip_combphy_pll_lock, priv, val,
288 val == grfcfg->pipe_pll_lock.enable,
289 10, 1000);
290 if (ret) {
291 dev_err(priv->dev, "wait phy PLL lock timeout\n");
292 goto error;
293 }
294
295 reset_control_deassert(priv->rsts[PHY_PIPE_RSTN]);
296 error:
297 return ret;
298 }
299
phy_u3_init(struct rockchip_combphy_priv * priv)300 static int phy_u3_init(struct rockchip_combphy_priv *priv)
301 {
302 const struct rockchip_combphy_grfcfg *grfcfg;
303 u32 val;
304 int ret = 0;
305
306 grfcfg = &priv->cfg->grfcfg;
307
308 /* Reset the USB3 controller first. */
309 reset_control_assert(priv->rsts[OTG_RSTN]);
310
311 reset_control_deassert(priv->rsts[PHY_POR_RSTN]);
312 /* Wait PHY power on stable. */
313 udelay(5);
314
315 reset_control_deassert(priv->rsts[PHY_APB_RSTN]);
316 udelay(5);
317
318 /*
319 * Start to configurate PHY registers for USB3.
320 * Note: set operation must be done before corresponding
321 * sel operation, otherwise, the PIPE PHY status lane0
322 * may be unable to get ready.
323 */
324
325 /* Disable PHY lane1 which isn't needed for USB3 */
326 param_write(priv->combphy_grf, &grfcfg->pipe_l1_set, true);
327 param_write(priv->combphy_grf, &grfcfg->pipe_l1_sel, true);
328
329 /* Set PHY Tx and Rx for USB3 */
330 param_write(priv->combphy_grf, &grfcfg->pipe_txrx_set, true);
331 param_write(priv->combphy_grf, &grfcfg->pipe_txrx_sel, true);
332
333 /* Set PHY PIPE MAC pclk request */
334 param_write(priv->combphy_grf, &grfcfg->pipe_clk_set, true);
335 param_write(priv->combphy_grf, &grfcfg->pipe_clk_sel, true);
336
337 /* Set PHY PIPE rate for USB3 */
338 param_write(priv->combphy_grf, &grfcfg->pipe_rate_set, true);
339 param_write(priv->combphy_grf, &grfcfg->pipe_rate_sel, true);
340
341 /* Set PHY mode for USB3 */
342 param_write(priv->combphy_grf, &grfcfg->pipe_mode_set, true);
343 param_write(priv->combphy_grf, &grfcfg->pipe_mode_sel, true);
344
345 /* Set PHY data bus width for USB3 */
346 param_write(priv->combphy_grf, &grfcfg->pipe_width_set, true);
347 param_write(priv->combphy_grf, &grfcfg->pipe_width_sel, true);
348
349 /* Select PIPE for USB3 */
350 param_write(priv->combphy_grf, &grfcfg->pipe_usb3_sel, true);
351
352 if (priv->cfg->combphy_cfg) {
353 ret = priv->cfg->combphy_cfg(priv);
354 if (ret)
355 goto error;
356 }
357
358 /* Wait Tx PLL lock */
359 usleep_range(300, 350);
360 ret = readx_poll_timeout_atomic(rockchip_combphy_pll_lock, priv, val,
361 val == grfcfg->pipe_pll_lock.enable,
362 10, 1000);
363 if (ret) {
364 dev_err(priv->dev, "wait phy PLL lock timeout\n");
365 goto error;
366 }
367
368 reset_control_deassert(priv->rsts[PHY_PIPE_RSTN]);
369
370 /* Wait PIPE PHY status lane0 ready */
371 ret = readx_poll_timeout_atomic(rockchip_combphy_is_ready, priv, val,
372 val == grfcfg->pipe_status_l0.enable,
373 10, 1000);
374 if (ret) {
375 dev_err(priv->dev, "wait phy status lane0 ready timeout\n");
376 goto error;
377 }
378
379 reset_control_deassert(priv->rsts[OTG_RSTN]);
380
381 error:
382 return ret;
383 }
384
rockchip_combphy_set_phy_type(struct rockchip_combphy_priv * priv)385 static int rockchip_combphy_set_phy_type(struct rockchip_combphy_priv *priv)
386 {
387 int ret = 0;
388
389 if (priv->phy_initialized)
390 return ret;
391
392 switch (priv->phy_type) {
393 case PHY_TYPE_PCIE:
394 ret = phy_pcie_init(priv);
395 break;
396 case PHY_TYPE_USB3:
397 ret = phy_u3_init(priv);
398 if (ret)
399 return ret;
400
401 /* Attributes */
402 ret = sysfs_create_group(&priv->dev->kobj,
403 &rockchip_combphy_u3phy_mode_attr_group);
404 break;
405 default:
406 dev_err(priv->dev, "incompatible PHY type\n");
407 return -EINVAL;
408 }
409
410 return ret;
411 }
412
rockchip_combphy_init(struct phy * phy)413 static int rockchip_combphy_init(struct phy *phy)
414 {
415 struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
416 int ret;
417
418 ret = clk_prepare_enable(priv->ref_clk);
419 if (ret) {
420 dev_err(priv->dev, "failed to enable ref_clk\n");
421 return ret;
422 }
423
424 ret = rockchip_combphy_set_phy_type(priv);
425 if (ret) {
426 dev_err(priv->dev, "failed to set phy type\n");
427 return ret;
428 }
429
430 priv->phy_initialized = true;
431
432 return 0;
433 }
434
rockchip_combphy_exit(struct phy * phy)435 static int rockchip_combphy_exit(struct phy *phy)
436 {
437 struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
438
439 /*
440 * Note: don't assert PHY reset here, because
441 * we set many phy configurations during phy
442 * init to reduce PHY power consumption, if we
443 * assert PHY reset here, these configurations
444 * will be lost, and increase power consumption.
445 */
446 clk_disable_unprepare(priv->ref_clk);
447
448 /* in case of waiting phy PLL lock timeout */
449 if (priv->phy_type == PHY_TYPE_PCIE) {
450 reset_control_assert(priv->rsts[PHY_GRF_P_RSTN]);
451 udelay(5);
452 reset_control_deassert(priv->rsts[PHY_GRF_P_RSTN]);
453 priv->phy_initialized = false;
454 }
455
456 return 0;
457 }
458
rockchip_combphy_power_on(struct phy * phy)459 static int rockchip_combphy_power_on(struct phy *phy)
460 {
461 struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
462 const struct rockchip_combphy_grfcfg *grfcfg;
463
464 if (!priv->phy_suspended)
465 return 0;
466
467 grfcfg = &priv->cfg->grfcfg;
468
469 if (priv->phy_type == PHY_TYPE_USB3) {
470 if (priv->cfg->combphy_low_power_ctrl)
471 priv->cfg->combphy_low_power_ctrl(priv, false);
472
473 /* Enable lane 0 squelch detection */
474 param_write(priv->combphy_grf, &grfcfg->pipe_l0rxelec_set,
475 false);
476
477 /*
478 * Check if lane 0 powerdown is already
479 * controlled by USB 3.0 controller.
480 */
481 if (param_read(priv->combphy_grf,
482 &grfcfg->pipe_l0pd_sel, 0))
483 goto done;
484
485 /* Exit to P0 from P3 */
486 param_write(priv->combphy_grf, &grfcfg->pipe_l0pd_p3, false);
487 usleep_range(250, 300);
488
489 /*
490 * Set lane 0 powerdown to be controlled
491 * by USB 3.0 controller.
492 */
493 param_write(priv->combphy_grf, &grfcfg->pipe_l0pd_sel, false);
494 }
495
496 done:
497 priv->phy_suspended = false;
498 return 0;
499 }
500
rockchip_combphy_power_off(struct phy * phy)501 static int rockchip_combphy_power_off(struct phy *phy)
502 {
503 struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
504 const struct rockchip_combphy_grfcfg *grfcfg;
505
506 if (priv->phy_suspended)
507 return 0;
508
509 grfcfg = &priv->cfg->grfcfg;
510
511 if (priv->phy_type == PHY_TYPE_USB3 ||
512 priv->phy_type == PHY_TYPE_PCIE) {
513 /*
514 * Check if lane 0 powerdown is already
515 * controlled by grf and in P3 state.
516 */
517 if (param_read(priv->combphy_grf,
518 &grfcfg->pipe_l0pd_sel, 1) &&
519 param_read(priv->combphy_grf,
520 &grfcfg->pipe_l0pd_p3, 3))
521 goto done;
522
523 /* Exit to P0 */
524 param_write(priv->combphy_grf, &grfcfg->pipe_l0pd_p3, false);
525 param_write(priv->combphy_grf, &grfcfg->pipe_l0pd_sel, true);
526 udelay(1);
527
528 /* Enter to P3 from P0 */
529 param_write(priv->combphy_grf, &grfcfg->pipe_l0pd_p3, true);
530 udelay(2);
531
532 /*
533 * Disable lane 0 squelch detection.
534 * Note: if squelch detection is disabled,
535 * the PHY can't detect LFPS.
536 */
537 param_write(priv->combphy_grf, &grfcfg->pipe_l0rxelec_set,
538 true);
539
540 if (priv->cfg->combphy_low_power_ctrl)
541 priv->cfg->combphy_low_power_ctrl(priv, true);
542 }
543
544 done:
545 priv->phy_suspended = true;
546 return 0;
547 }
548
rockchip_combphy_set_mode(struct phy * phy,enum phy_mode mode,int submode)549 static int rockchip_combphy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
550 {
551 struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
552 u32 reg;
553
554 if (priv->phy_type != PHY_TYPE_PCIE)
555 return -EINVAL;
556
557 reg = readl(priv->mmio + 0x21a8);
558
559 if (PHY_MODE_PCIE_EP == submode)
560 reg |= (0x1 << 2);
561 else if (PHY_MODE_PCIE_RC == submode)
562 reg &= ~(0x1 << 2);
563 else
564 return -EINVAL;
565
566 writel(reg, priv->mmio + 0x21a8);
567 return 0;
568 }
569
570 static const struct phy_ops rockchip_combphy_ops = {
571 .init = rockchip_combphy_init,
572 .exit = rockchip_combphy_exit,
573 .power_on = rockchip_combphy_power_on,
574 .power_off = rockchip_combphy_power_off,
575 .set_mode = rockchip_combphy_set_mode,
576 .owner = THIS_MODULE,
577 };
578
rockchip_combphy_xlate(struct device * dev,struct of_phandle_args * args)579 static struct phy *rockchip_combphy_xlate(struct device *dev,
580 struct of_phandle_args *args)
581 {
582 struct rockchip_combphy_priv *priv = dev_get_drvdata(dev);
583
584 if (args->args_count < 1) {
585 dev_err(dev, "invalid number of arguments\n");
586 return ERR_PTR(-EINVAL);
587 }
588
589 if (priv->phy_type != PHY_NONE && priv->phy_type != args->args[0]) {
590 dev_err(dev, "type select %d overwriting phy type %d\n",
591 args->args[0], priv->phy_type);
592 return ERR_PTR(-ENODEV);
593 }
594
595 priv->phy_type = args->args[0];
596
597 if (priv->phy_type < PHY_TYPE_SATA || priv->phy_type > PHY_TYPE_USB3) {
598 dev_err(dev, "invalid phy type select argument\n");
599 return ERR_PTR(-EINVAL);
600 }
601
602 return priv->phy;
603 }
604
rockchip_combphy_parse_dt(struct device * dev,struct rockchip_combphy_priv * priv)605 static int rockchip_combphy_parse_dt(struct device *dev,
606 struct rockchip_combphy_priv *priv)
607 {
608 u32 i;
609
610 priv->combphy_grf = syscon_regmap_lookup_by_phandle(dev->of_node,
611 "rockchip,combphygrf");
612 if (IS_ERR(priv->combphy_grf)) {
613 dev_err(dev, "failed to find combphy grf regmap\n");
614 return PTR_ERR(priv->combphy_grf);
615 }
616
617 priv->usb_pcie_grf = syscon_regmap_lookup_by_phandle(dev->of_node,
618 "rockchip,usbpciegrf");
619 if (IS_ERR(priv->usb_pcie_grf)) {
620 dev_err(dev, "failed to find usb_pcie_grf regmap\n");
621 return PTR_ERR(priv->usb_pcie_grf);
622 }
623
624 priv->ref_clk = devm_clk_get(dev, "refclk");
625 if (IS_ERR(priv->ref_clk)) {
626 dev_err(dev, "failed to find ref clock\n");
627 return PTR_ERR(priv->ref_clk);
628 }
629
630 for (i = 0; i < PHY_RESET_MAX; i++) {
631 priv->rsts[i] = devm_reset_control_get(dev, get_reset_name(i));
632 if (IS_ERR(priv->rsts[i])) {
633 dev_warn(dev, "no %s reset control specified\n",
634 get_reset_name(i));
635 priv->rsts[i] = NULL;
636 }
637 }
638
639 return 0;
640 }
641
rockchip_combphy_probe(struct platform_device * pdev)642 static int rockchip_combphy_probe(struct platform_device *pdev)
643 {
644 struct phy_provider *phy_provider;
645 struct device *dev = &pdev->dev;
646 struct rockchip_combphy_priv *priv;
647 struct resource *res;
648 const struct rockchip_combphy_cfg *phy_cfg;
649 int ret;
650
651 phy_cfg = of_device_get_match_data(dev);
652 if (!phy_cfg) {
653 dev_err(dev, "No OF match data provided\n");
654 return -EINVAL;
655 }
656
657 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
658 if (!priv)
659 return -ENOMEM;
660
661 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
662 priv->mmio = devm_ioremap_resource(dev, res);
663 if (IS_ERR(priv->mmio)) {
664 ret = PTR_ERR(priv->mmio);
665 return ret;
666 }
667
668 ret = rockchip_combphy_parse_dt(dev, priv);
669 if (ret) {
670 dev_err(dev, "parse dt failed, ret(%d)\n", ret);
671 return ret;
672 }
673
674 reset_control_assert(priv->rsts[PHY_POR_RSTN]);
675 reset_control_assert(priv->rsts[PHY_APB_RSTN]);
676 reset_control_assert(priv->rsts[PHY_PIPE_RSTN]);
677
678 priv->phy_type = PHY_NONE;
679 priv->dev = dev;
680 priv->cfg = phy_cfg;
681 priv->phy = devm_phy_create(dev, NULL, &rockchip_combphy_ops);
682 if (IS_ERR(priv->phy)) {
683 dev_err(dev, "failed to create combphy\n");
684 return PTR_ERR(priv->phy);
685 }
686
687 dev_set_drvdata(dev, priv);
688 phy_set_drvdata(priv->phy, priv);
689
690 phy_provider = devm_of_phy_provider_register(dev,
691 rockchip_combphy_xlate);
692 return PTR_ERR_OR_ZERO(phy_provider);
693 }
694
rockchip_combphy_remove(struct platform_device * pdev)695 static int rockchip_combphy_remove(struct platform_device *pdev)
696 {
697 struct rockchip_combphy_priv *priv = platform_get_drvdata(pdev);
698
699 if (priv->phy_type == PHY_TYPE_USB3 && priv->phy_initialized)
700 sysfs_remove_group(&priv->dev->kobj,
701 &rockchip_combphy_u3phy_mode_attr_group);
702
703 return 0;
704 }
705
rk1808_combphy_cfg(struct rockchip_combphy_priv * priv)706 static int rk1808_combphy_cfg(struct rockchip_combphy_priv *priv)
707 {
708 unsigned long rate;
709 u32 reg;
710 bool ssc_en = false;
711
712 rate = clk_get_rate(priv->ref_clk);
713
714 /* Configure PHY reference clock frequency */
715 switch (rate) {
716 case 24000000:
717 /*
718 * The default PHY refclk frequency
719 * configuration is 24MHz.
720 */
721 break;
722 case 25000000:
723 writel(0x00, priv->mmio + 0x2118);
724 writel(0x64, priv->mmio + 0x211c);
725 writel(0x01, priv->mmio + 0x2020);
726 writel(0x64, priv->mmio + 0x2028);
727 writel(0x21, priv->mmio + 0x2030);
728
729 if (priv->phy_type == PHY_TYPE_PCIE) {
730 writel(0x1, priv->mmio + 0x3020);
731 writel(0x64, priv->mmio + 0x3028);
732 writel(0x21, priv->mmio + 0x3030);
733 }
734
735 break;
736 case 50000000:
737 writel(0x00, priv->mmio + 0x2118);
738 writel(0x32, priv->mmio + 0x211c);
739 writel(0x01, priv->mmio + 0x2020);
740 writel(0x32, priv->mmio + 0x2028);
741 writel(0x21, priv->mmio + 0x2030);
742 break;
743 default:
744 dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
745 return -EINVAL;
746 }
747
748 if (priv->phy_type == PHY_TYPE_PCIE) {
749 /* turn on pcie phy pd */
750 writel(0x08400000, priv->mmio + 0x0);
751 writel(0x03030000, priv->mmio + 0x8);
752
753 /* Adjust Lane 0 Rx interface timing */
754 writel(0x20, priv->mmio + 0x20ac);
755 writel(0x12, priv->mmio + 0x20c8);
756 writel(0x76, priv->mmio + 0x2150);
757
758 /* Adjust Lane 1 Rx interface timing */
759 writel(0x20, priv->mmio + 0x30ac);
760 writel(0x12, priv->mmio + 0x30c8);
761 writel(0x76, priv->mmio + 0x3150);
762 /* Set PHY output refclk path */
763 writel(0x0, priv->mmio + 0x21a4);
764 writel(0x0, priv->mmio + 0x21a8);
765 writel(0xb, priv->mmio + 0x21ec);
766
767 /* Physical ordered set for PCIe */
768 writel(0x02, priv->mmio + 0x45c0);
769 writel(0x83, priv->mmio + 0x45c4);
770 writel(0x03, priv->mmio + 0x45c8);
771 writel(0x43, priv->mmio + 0x45cc);
772 writel(0x00, priv->mmio + 0x45d0);
773 writel(0xbc, priv->mmio + 0x45d4);
774
775 /* Boost pre-emphasis */
776 writel(0xaa, priv->mmio + 0x21b8);
777 writel(0xaa, priv->mmio + 0x31b8);
778 } else if (priv->phy_type == PHY_TYPE_USB3) {
779 /*
780 * Disable PHY Lane 1 which isn't needed
781 * for USB3 to reduce power consumption.
782 */
783 /* Lane 1 cdr power down */
784 writel(0x09, priv->mmio + 0x3148);
785
786 /* Lane 1 rx bias disable */
787 writel(0x01, priv->mmio + 0x21cc);
788
789 /* Lane 1 cdr disable */
790 writel(0x08, priv->mmio + 0x30c4);
791 writel(0x08, priv->mmio + 0x20f4);
792
793 /* Lane 1 rx lock disable and tx bias disable */
794 writel(0x12, priv->mmio + 0x3150);
795
796 /* Lane 1 rx termination disable, and tx_cmenb disable */
797 writel(0x04, priv->mmio + 0x3080);
798
799 /* Lane 1 tx termination disable */
800 writel(0x1d, priv->mmio + 0x3090);
801
802 /* Lane 1 tx driver disable */
803 writel(0x50, priv->mmio + 0x21c4);
804 writel(0x10, priv->mmio + 0x2050);
805
806 /* Lane 1 txldo_refsel disable */
807 writel(0x81, priv->mmio + 0x31a8);
808
809 /* Lane 1 txdetrx_en disable */
810 writel(0x00, priv->mmio + 0x31e8);
811
812 /* Lane 1 rxcm_en disable */
813 writel(0x08, priv->mmio + 0x30c0);
814
815 /* Adjust Lane 0 Rx interface timing */
816 writel(0x20, priv->mmio + 0x20ac);
817
818 /* Set and enable SSC */
819 switch (rate) {
820 case 24000000:
821 /* Set SSC rate to 31.25KHz */
822 reg = readl(priv->mmio + 0x2108);
823 reg = (reg & ~0xf) | 0x1;
824 writel(reg, priv->mmio + 0x2108);
825 ssc_en = true;
826 break;
827 case 25000000:
828 /* Set SSC rate to 32.55KHz */
829 reg = readl(priv->mmio + 0x2108);
830 reg = (reg & ~0xf) | 0x6;
831 writel(reg, priv->mmio + 0x2108);
832 ssc_en = true;
833 break;
834 default:
835 dev_warn(priv->dev,
836 "failed to set SSC on rate: %lu\n", rate);
837 break;
838 }
839
840 if (ssc_en) {
841 /* Enable SSC */
842 reg = readl(priv->mmio + 0x2120);
843 reg &= ~BIT(4);
844 writel(reg, priv->mmio + 0x2120);
845
846 reg = readl(priv->mmio + 0x2000);
847 reg &= ~0x6;
848 writel(reg, priv->mmio + 0x2000);
849 }
850
851 /*
852 * Tuning Tx:
853 * offset 0x21b8 bit[7:4]: lane 0 TX driver swing
854 * tuning bits with weight, "1111" represents the
855 * largest swing and "0000" the smallest.
856 */
857 reg = readl(priv->mmio + 0x21b8);
858 reg = (reg & ~0xf0) | 0xe0;
859 writel(reg, priv->mmio + 0x21b8);
860
861 /*
862 * Tuning Rx for RJTL:
863 * Decrease CDR Chump Bump current.
864 */
865 reg = readl(priv->mmio + 0x20c8);
866 reg = (reg & ~0x6) | BIT(1);
867 writel(reg, priv->mmio + 0x20c8);
868 reg = readl(priv->mmio + 0x2150);
869 reg |= BIT(2);
870 writel(reg, priv->mmio + 0x2150);
871 } else {
872 dev_err(priv->dev, "failed to cfg incompatible PHY type\n");
873 return -EINVAL;
874 }
875
876 return 0;
877 }
878
rk1808_combphy_low_power_control(struct rockchip_combphy_priv * priv,bool en)879 static int rk1808_combphy_low_power_control(struct rockchip_combphy_priv *priv,
880 bool en)
881 {
882 if (priv->phy_type != PHY_TYPE_USB3) {
883 /* turn off pcie phy pd */
884 writel(0x08400840, priv->mmio + 0x0);
885 writel(0x03030303, priv->mmio + 0x8);
886
887 /* enter PCIe phy low power mode */
888 writel(0x36, priv->mmio + 0x2150);
889 writel(0x36, priv->mmio + 0x3150);
890 writel(0x02, priv->mmio + 0x21e8);
891 writel(0x02, priv->mmio + 0x31e8);
892 writel(0x0c, priv->mmio + 0x2080);
893 writel(0x0c, priv->mmio + 0x3080);
894 writel(0x08, priv->mmio + 0x20c0);
895 writel(0x08, priv->mmio + 0x30c0);
896 writel(0x08, priv->mmio + 0x2058);
897
898 writel(0x10, priv->mmio + 0x2044);
899 writel(0x10, priv->mmio + 0x21a8);
900 writel(0x10, priv->mmio + 0x31a8);
901 writel(0x08, priv->mmio + 0x2058);
902 writel(0x08, priv->mmio + 0x3058);
903 writel(0x40, priv->mmio + 0x205c);
904 writel(0x40, priv->mmio + 0x305c);
905 writel(0x08, priv->mmio + 0x2184);
906 writel(0x08, priv->mmio + 0x3184);
907 writel(0x00, priv->mmio + 0x2150);
908 writel(0x00, priv->mmio + 0x3150);
909 writel(0x10, priv->mmio + 0x20e0);
910 writel(0x00, priv->mmio + 0x21e8);
911 writel(0x00, priv->mmio + 0x31e8);
912
913 return 0;
914 }
915
916 if (en) {
917 /* Lane 0 tx_biasen disable */
918 writel(0x36, priv->mmio + 0x2150);
919
920 /* Lane 0 txdetrx_en disable */
921 writel(0x02, priv->mmio + 0x21e8);
922
923 /* Lane 0 tx_cmenb disable */
924 writel(0x0c, priv->mmio + 0x2080);
925
926 /* Lane 0 rxcm_en disable */
927 writel(0x08, priv->mmio + 0x20c0);
928
929 /* Lane 0 and Lane 1 bg_pwrdn */
930 writel(0x10, priv->mmio + 0x2044);
931
932 /* Lane 0 and Lane 1 rcomp_osenseampen disable */
933 writel(0x08, priv->mmio + 0x2058);
934
935 /* Lane 0 txldo_refsel disable and LDO disable */
936 writel(0x91, priv->mmio + 0x21a8);
937
938 /* Lane 1 LDO disable */
939 writel(0x91, priv->mmio + 0x31a8);
940 } else {
941 /* Lane 0 tx_biasen enable */
942 writel(0x76, priv->mmio + 0x2150);
943
944 /* Lane 0 txdetrx_en enable */
945 writel(0x02, priv->mmio + 0x21e8);
946
947 /* Lane 0 tx_cmenb enable */
948 writel(0x08, priv->mmio + 0x2080);
949
950 /* Lane 0 rxcm_en enable */
951 writel(0x18, priv->mmio + 0x20c0);
952
953 /* Lane 0 and Lane 1 bg_pwrdn */
954 writel(0x00, priv->mmio + 0x2044);
955
956 /* Lane 0 and Lane 1 rcomp_osenseampen enable */
957 writel(0x28, priv->mmio + 0x2058);
958
959 /* Lane 0 txldo_refsel enable and LDO enable */
960 writel(0x01, priv->mmio + 0x21a8);
961
962 /* Lane 1 LDO enable */
963 writel(0x81, priv->mmio + 0x31a8);
964 }
965
966 return 0;
967 }
968
969 static const struct rockchip_combphy_cfg rk1808_combphy_cfgs = {
970 .grfcfg = {
971 .pipe_l1_sel = { 0x0000, 15, 11, 0x00, 0x1f },
972 .pipe_l1_set = { 0x0008, 13, 8, 0x00, 0x13 },
973 .pipe_l1rxterm_sel = { 0x0000, 12, 12, 0x0, 0x1 },
974 .pipe_l1pd_sel = { 0x0000, 11, 11, 0x0, 0x1},
975 .pipe_l1pd_p3 = { 0x0008, 9, 8, 0x0, 0x3 },
976 .pipe_l0rxterm_sel = { 0x0000, 7, 7, 0x0, 0x1 },
977 .pipe_l0pd_sel = { 0x0000, 6, 6, 0x0, 0x1 },
978 .pipe_l0pd_p3 = { 0x0008, 1, 0, 0x0, 0x3 },
979 .pipe_clk_sel = { 0x0000, 3, 3, 0x0, 0x1 },
980 .pipe_clk_set = { 0x0004, 7, 6, 0x1, 0x0 },
981 .pipe_rate_sel = { 0x0000, 2, 2, 0x0, 0x1 },
982 .pipe_rate_set = { 0x0004, 5, 4, 0x0, 0x1 },
983 .pipe_mode_sel = { 0x0000, 1, 1, 0x0, 0x1 },
984 .pipe_mode_set = { 0x0004, 3, 2, 0x0, 0x1 },
985 .pipe_txrx_sel = { 0x0004, 15, 8, 0x10, 0x2f },
986 .pipe_txrx_set = { 0x0008, 15, 14, 0x0, 0x3 },
987 .pipe_l1rxterm_set = { 0x0008, 10, 10, 0x0, 0x1 },
988 .pipe_l0rxterm_set = { 0x0008, 2, 2, 0x0, 0x1 },
989 .pipe_l0rxelec_set = { 0x0008, 6, 6, 0x0, 0x1 },
990 .pipe_width_sel = { 0x0000, 0, 0, 0x0, 0x1 },
991 .pipe_width_set = { 0x0004, 1, 0, 0x2, 0x0 },
992 .pipe_usb3_sel = { 0x000c, 0, 0, 0x0, 0x1 },
993 .pipe_pll_lock = { 0x0034, 14, 14, 0x0, 0x1 },
994 .pipe_status_l0 = { 0x0034, 7, 7, 0x1, 0x0 },
995 .u3_port_disable = { 0x0434, 0, 0, 0, 1},
996 .u3_port_num = { 0x0434, 15, 12, 0, 1},
997 },
998 .combphy_cfg = rk1808_combphy_cfg,
999 .combphy_low_power_ctrl = rk1808_combphy_low_power_control,
1000 };
1001
1002 static const struct of_device_id rockchip_combphy_of_match[] = {
1003 {
1004 .compatible = "rockchip,rk1808-combphy",
1005 .data = &rk1808_combphy_cfgs,
1006 },
1007 { },
1008 };
1009
1010 MODULE_DEVICE_TABLE(of, rockchip_combphy_of_match);
1011
1012 static struct platform_driver rockchip_combphy_driver = {
1013 .probe = rockchip_combphy_probe,
1014 .remove = rockchip_combphy_remove,
1015 .driver = {
1016 .name = "rockchip-combphy",
1017 .of_match_table = rockchip_combphy_of_match,
1018 },
1019 };
1020 module_platform_driver(rockchip_combphy_driver);
1021
1022 MODULE_AUTHOR("William Wu <william.wu@rock-chips.com>");
1023 MODULE_DESCRIPTION("Rockchip USB3.0 and PCIE COMBPHY driver");
1024 MODULE_LICENSE("GPL v2");
1025