1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Rockchip USBDP Combo PHY with Samsung IP block driver
4 *
5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/delay.h>
12 #include <linux/gpio.h>
13 #include <linux/io.h>
14 #include <linux/iopoll.h>
15 #include <linux/kernel.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
19 #include <linux/of.h>
20 #include <linux/of_address.h>
21 #include <linux/of_platform.h>
22 #include <linux/phy/phy.h>
23 #include <linux/platform_device.h>
24 #include <linux/regmap.h>
25 #include <linux/reset.h>
26 #include <linux/usb/ch9.h>
27 #include <linux/usb/typec_dp.h>
28 #include <linux/usb/typec_mux.h>
29
30 #include <linux/phy/phy-rockchip-usbdp.h>
31
32 #define BIT_WRITEABLE_SHIFT 16
33
34 enum {
35 DP_BW_RBR,
36 DP_BW_HBR,
37 DP_BW_HBR2,
38 DP_BW_HBR3,
39 };
40
41 enum {
42 UDPHY_MODE_NONE = 0,
43 UDPHY_MODE_USB = BIT(0),
44 UDPHY_MODE_DP = BIT(1),
45 UDPHY_MODE_DP_USB = BIT(1) | BIT(0),
46 };
47
48 struct udphy_grf_reg {
49 unsigned int offset;
50 unsigned int bitend;
51 unsigned int bitstart;
52 unsigned int disable;
53 unsigned int enable;
54 };
55
56 struct udphy_grf_cfg {
57 /* u2phy-grf */
58 struct udphy_grf_reg bvalid_phy_con;
59 struct udphy_grf_reg bvalid_grf_con;
60
61 /* usb-grf */
62 struct udphy_grf_reg usb3otg0_cfg;
63 struct udphy_grf_reg usb3otg1_cfg;
64
65 /* usbdpphy-grf */
66 struct udphy_grf_reg low_pwrn;
67 struct udphy_grf_reg rx_lfps;
68 };
69
70 struct udphy_vogrf_cfg {
71 /* vo-grf */
72 struct udphy_grf_reg hpd_trigger;
73 };
74
75 struct rockchip_udphy;
76
77 struct rockchip_udphy_cfg {
78 /* resets to be requested */
79 const char * const *rst_list;
80 int num_rsts;
81
82 struct udphy_grf_cfg grfcfg;
83 struct udphy_vogrf_cfg vogrfcfg[2];
84 int (*combophy_init)(struct rockchip_udphy *udphy);
85 int (*dp_phy_set_rate)(struct rockchip_udphy *udphy,
86 struct phy_configure_opts_dp *dp);
87 int (*dp_phy_set_voltages)(struct rockchip_udphy *udphy,
88 struct phy_configure_opts_dp *dp);
89 int (*hpd_event_trigger)(struct rockchip_udphy *udphy, bool hpd);
90 int (*dplane_enable)(struct rockchip_udphy *udphy, int dp_lanes);
91 int (*dplane_select)(struct rockchip_udphy *udphy);
92 };
93
94 struct rockchip_udphy {
95 struct device *dev;
96 struct regmap *pma_regmap;
97 struct regmap *u2phygrf;
98 struct regmap *udphygrf;
99 struct regmap *usbgrf;
100 struct regmap *vogrf;
101 struct typec_switch *sw;
102 struct typec_mux *mux;
103 struct mutex mutex; /* mutex to protect access to individual PHYs */
104
105 /* clocks and rests */
106 int num_clks;
107 struct clk_bulk_data *clks;
108 struct clk *refclk;
109 struct reset_control **rsts;
110
111 /* PHY status management */
112 bool flip;
113 bool mode_change;
114 u8 mode;
115 u8 status;
116
117 /* utilized for USB */
118 bool hs; /* flag for high-speed */
119
120 /* utilized for DP */
121 struct gpio_desc *sbu1_dc_gpio;
122 struct gpio_desc *sbu2_dc_gpio;
123 u32 lane_mux_sel[4];
124 u32 dp_lane_sel[4];
125 u32 dp_aux_dout_sel;
126 u32 dp_aux_din_sel;
127 int id;
128
129 /* PHY const config */
130 const struct rockchip_udphy_cfg *cfgs;
131 };
132
133 static const struct reg_sequence rk3588_udphy_24m_refclk_cfg[] = {
134 {0x0090, 0x68}, {0x0094, 0x68},
135 {0x0128, 0x24}, {0x012c, 0x44},
136 {0x0130, 0x3f}, {0x0134, 0x44},
137 {0x015c, 0xa9}, {0x0160, 0x71},
138 {0x0164, 0x71}, {0x0168, 0xa9},
139 {0x0174, 0xa9}, {0x0178, 0x71},
140 {0x017c, 0x71}, {0x0180, 0xa9},
141 {0x018c, 0x41}, {0x0190, 0x00},
142 {0x0194, 0x05}, {0x01ac, 0x2a},
143 {0x01b0, 0x17}, {0x01b4, 0x17},
144 {0x01b8, 0x2a}, {0x01c8, 0x04},
145 {0x01cc, 0x08}, {0x01d0, 0x08},
146 {0x01d4, 0x04}, {0x01d8, 0x20},
147 {0x01dc, 0x01}, {0x01e0, 0x09},
148 {0x01e4, 0x03}, {0x01f0, 0x29},
149 {0x01f4, 0x02}, {0x01f8, 0x02},
150 {0x01fc, 0x29}, {0x0208, 0x2a},
151 {0x020c, 0x17}, {0x0210, 0x17},
152 {0x0214, 0x2a}, {0x0224, 0x20},
153 {0x03f0, 0x0d}, {0x03f4, 0x09},
154 {0x03f8, 0x09}, {0x03fc, 0x0d},
155 {0x0404, 0x0e}, {0x0408, 0x14},
156 {0x040c, 0x14}, {0x0410, 0x3b},
157 {0x0ce0, 0x68}, {0x0ce8, 0xd0},
158 {0x0cf0, 0x87}, {0x0cf8, 0x70},
159 {0x0d00, 0x70}, {0x0d08, 0xa9},
160 {0x1ce0, 0x68}, {0x1ce8, 0xd0},
161 {0x1cf0, 0x87}, {0x1cf8, 0x70},
162 {0x1d00, 0x70}, {0x1d08, 0xa9},
163 {0x0a3c, 0xd0}, {0x0a44, 0xd0},
164 {0x0a48, 0x01}, {0x0a4c, 0x0d},
165 {0x0a54, 0xe0}, {0x0a5c, 0xe0},
166 {0x0a64, 0xa8}, {0x1a3c, 0xd0},
167 {0x1a44, 0xd0}, {0x1a48, 0x01},
168 {0x1a4c, 0x0d}, {0x1a54, 0xe0},
169 {0x1a5c, 0xe0}, {0x1a64, 0xa8}
170 };
171
172 static const struct reg_sequence rk3588_udphy_26m_refclk_cfg[] = {
173 {0x0830, 0x07}, {0x085c, 0x80},
174 {0x1030, 0x07}, {0x105c, 0x80},
175 {0x1830, 0x07}, {0x185c, 0x80},
176 {0x2030, 0x07}, {0x205c, 0x80},
177 {0x0228, 0x38}, {0x0104, 0x44},
178 {0x0248, 0x44}, {0x038C, 0x02},
179 {0x0878, 0x04}, {0x1878, 0x04},
180 {0x0898, 0x77}, {0x1898, 0x77},
181 {0x0054, 0x01}, {0x00e0, 0x38},
182 {0x0060, 0x24}, {0x0064, 0x77},
183 {0x0070, 0x76}, {0x0234, 0xE8},
184 {0x0AF4, 0x15}, {0x1AF4, 0x15},
185 {0x081C, 0xE5}, {0x181C, 0xE5},
186 {0x099C, 0x48}, {0x199C, 0x48},
187 {0x09A4, 0x07}, {0x09A8, 0x22},
188 {0x19A4, 0x07}, {0x19A8, 0x22},
189 {0x09B8, 0x3E}, {0x19B8, 0x3E},
190 {0x09E4, 0x02}, {0x19E4, 0x02},
191 {0x0A34, 0x1E}, {0x1A34, 0x1E},
192 {0x0A98, 0x2F}, {0x1A98, 0x2F},
193 {0x0c30, 0x0E}, {0x0C48, 0x06},
194 {0x1C30, 0x0E}, {0x1C48, 0x06},
195 {0x028C, 0x18}, {0x0AF0, 0x00},
196 {0x1AF0, 0x00}
197 };
198
199 static const struct reg_sequence rk3588_udphy_init_sequence[] = {
200 {0x0104, 0x44}, {0x0234, 0xE8},
201 {0x0248, 0x44}, {0x028C, 0x18},
202 {0x081C, 0xE5}, {0x0878, 0x00},
203 {0x0994, 0x1C}, {0x0AF0, 0x00},
204 {0x181C, 0xE5}, {0x1878, 0x00},
205 {0x1994, 0x1C}, {0x1AF0, 0x00},
206 {0x0428, 0x60}, {0x0D58, 0x33},
207 {0x1D58, 0x33}, {0x0990, 0x74},
208 {0x0D64, 0x17}, {0x08C8, 0x13},
209 {0x1990, 0x74}, {0x1D64, 0x17},
210 {0x18C8, 0x13}, {0x0D90, 0x40},
211 {0x0DA8, 0x40}, {0x0DC0, 0x40},
212 {0x0DD8, 0x40}, {0x1D90, 0x40},
213 {0x1DA8, 0x40}, {0x1DC0, 0x40},
214 {0x1DD8, 0x40}, {0x03C0, 0x30},
215 {0x03C4, 0x06}, {0x0E10, 0x00},
216 {0x1E10, 0x00}, {0x043C, 0x0F},
217 {0x0D2C, 0xFF}, {0x1D2C, 0xFF},
218 {0x0D34, 0x0F}, {0x1D34, 0x0F},
219 {0x08FC, 0x2A}, {0x0914, 0x28},
220 {0x0A30, 0x03}, {0x0E38, 0x05},
221 {0x0ECC, 0x27}, {0x0ED0, 0x22},
222 {0x0ED4, 0x26}, {0x18FC, 0x2A},
223 {0x1914, 0x28}, {0x1A30, 0x03},
224 {0x1E38, 0x05}, {0x1ECC, 0x27},
225 {0x1ED0, 0x22}, {0x1ED4, 0x26},
226 {0x0048, 0x0F}, {0x0060, 0x3C},
227 {0x0064, 0xF7}, {0x006C, 0x20},
228 {0x0070, 0x7D}, {0x0074, 0x68},
229 {0x0AF4, 0x1A}, {0x1AF4, 0x1A},
230 {0x0440, 0x3F}, {0x10D4, 0x08},
231 {0x20D4, 0x08}, {0x00D4, 0x30},
232 {0x0024, 0x6e},
233 };
234
grfreg_write(struct regmap * base,const struct udphy_grf_reg * reg,bool en)235 static inline int grfreg_write(struct regmap *base,
236 const struct udphy_grf_reg *reg, bool en)
237 {
238 u32 val, mask, tmp;
239
240 tmp = en ? reg->enable : reg->disable;
241 mask = GENMASK(reg->bitend, reg->bitstart);
242 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
243
244 return regmap_write(base, reg->offset, val);
245 }
246
udphy_clk_init(struct rockchip_udphy * udphy,struct device * dev)247 static int udphy_clk_init(struct rockchip_udphy *udphy, struct device *dev)
248 {
249 int i;
250
251 udphy->num_clks = devm_clk_bulk_get_all(dev, &udphy->clks);
252 if (udphy->num_clks < 1)
253 return -ENODEV;
254
255 /* used for configure phy reference clock frequency */
256 for (i = 0; i < udphy->num_clks; i++) {
257 if (!strncmp(udphy->clks[i].id, "refclk", 6)) {
258 udphy->refclk = udphy->clks[i].clk;
259 break;
260 }
261 }
262
263 if (!udphy->refclk)
264 dev_warn(udphy->dev, "no refclk found\n");
265
266 return 0;
267 }
268
udphy_reset_init(struct rockchip_udphy * udphy,struct device * dev)269 static int udphy_reset_init(struct rockchip_udphy *udphy, struct device *dev)
270 {
271 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
272 int idx;
273
274 udphy->rsts = devm_kcalloc(dev, cfg->num_rsts,
275 sizeof(*udphy->rsts), GFP_KERNEL);
276 if (!udphy->rsts)
277 return -ENOMEM;
278
279 for (idx = 0; idx < cfg->num_rsts; idx++) {
280 struct reset_control *rst;
281 const char *name = cfg->rst_list[idx];
282
283 rst = devm_reset_control_get(dev, name);
284 if (IS_ERR(rst)) {
285 dev_err(dev, "failed to get %s reset\n", name);
286 devm_kfree(dev, (void *)udphy->rsts);
287 return PTR_ERR(rst);
288 }
289
290 udphy->rsts[idx] = rst;
291 reset_control_assert(udphy->rsts[idx]);
292 }
293
294 return 0;
295 }
296
udphy_get_rst_idx(const char * const * list,int num,char * name)297 static int udphy_get_rst_idx(const char * const *list, int num, char *name)
298 {
299 int idx;
300
301 for (idx = 0; idx < num; idx++) {
302 if (!strcmp(list[idx], name))
303 return idx;
304 }
305
306 return -EINVAL;
307 }
308
udphy_reset_assert(struct rockchip_udphy * udphy,char * name)309 static int udphy_reset_assert(struct rockchip_udphy *udphy, char *name)
310 {
311 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
312 int idx;
313
314 idx = udphy_get_rst_idx(cfg->rst_list, cfg->num_rsts, name);
315 if (idx < 0)
316 return idx;
317
318 return reset_control_assert(udphy->rsts[idx]);
319 }
320
udphy_reset_deassert(struct rockchip_udphy * udphy,char * name)321 static int udphy_reset_deassert(struct rockchip_udphy *udphy, char *name)
322 {
323 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
324 int idx;
325
326 idx = udphy_get_rst_idx(cfg->rst_list, cfg->num_rsts, name);
327 if (idx < 0)
328 return idx;
329
330 return reset_control_deassert(udphy->rsts[idx]);
331 }
332
udphy_u3_port_disable(struct rockchip_udphy * udphy,u8 disable)333 static void udphy_u3_port_disable(struct rockchip_udphy *udphy, u8 disable)
334 {
335 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
336 const struct udphy_grf_reg *preg;
337
338 preg = udphy->id ? &cfg->grfcfg.usb3otg1_cfg : &cfg->grfcfg.usb3otg0_cfg;
339 grfreg_write(udphy->usbgrf, preg, disable);
340 }
341
udphy_usb_bvalid_enable(struct rockchip_udphy * udphy,u8 enable)342 static void udphy_usb_bvalid_enable(struct rockchip_udphy *udphy, u8 enable)
343 {
344 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
345
346 grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_phy_con, enable);
347 grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_grf_con, enable);
348 }
349
350 /*
351 * In usb/dp combo phy driver, here are 2 ways to mapping lanes.
352 *
353 * 1 Type-C Mapping table (DP_Alt_Mode V1.0b remove ABF pin mapping)
354 * ---------------------------------------------------------------------------
355 * Type-C Pin B11-B10 A2-A3 A11-A10 B2-B3
356 * PHY Pad ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
357 * C/E(Normal) dpln3 dpln2 dpln0 dpln1
358 * C/E(Flip ) dpln0 dpln1 dpln3 dpln2
359 * D/F(Normal) usbrx usbtx dpln0 dpln1
360 * D/F(Flip ) dpln0 dpln1 usbrx usbtx
361 * A(Normal ) dpln3 dpln1 dpln2 dpln0
362 * A(Flip ) dpln2 dpln0 dpln3 dpln1
363 * B(Normal ) usbrx usbtx dpln1 dpln0
364 * B(Flip ) dpln1 dpln0 usbrx usbtx
365 * ---------------------------------------------------------------------------
366 *
367 * 2 Mapping the lanes in dtsi
368 * if all 4 lane assignment for dp function, define rockchip,dp-lane-mux = <x x x x>;
369 * sample as follow:
370 * ---------------------------------------------------------------------------
371 * B11-B10 A2-A3 A11-A10 B2-B3
372 * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
373 * <0 1 2 3> dpln0 dpln1 dpln2 dpln3
374 * <2 3 0 1> dpln2 dpln3 dpln0 dpln1
375 * ---------------------------------------------------------------------------
376 * if 2 lane for dp function, 2 lane for usb function, define rockchip,dp-lane-mux = <x x>;
377 * sample as follow:
378 * ---------------------------------------------------------------------------
379 * B11-B10 A2-A3 A11-A10 B2-B3
380 * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
381 * <0 1> dpln0 dpln1 usbrx usbtx
382 * <2 3> usbrx usbtx dpln0 dpln1
383 * ---------------------------------------------------------------------------
384 */
385
udphy_dplane_select(struct rockchip_udphy * udphy)386 static int udphy_dplane_select(struct rockchip_udphy *udphy)
387 {
388 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
389
390 if (cfg->dplane_select)
391 return cfg->dplane_select(udphy);
392
393 return 0;
394 }
395
udphy_dplane_get(struct rockchip_udphy * udphy)396 static int udphy_dplane_get(struct rockchip_udphy *udphy)
397 {
398 int dp_lanes;
399
400 switch (udphy->mode) {
401 case UDPHY_MODE_DP:
402 dp_lanes = 4;
403 break;
404 case UDPHY_MODE_DP_USB:
405 dp_lanes = 2;
406 break;
407 case UDPHY_MODE_USB:
408 fallthrough;
409 default:
410 dp_lanes = 0;
411 break;
412 }
413
414 return dp_lanes;
415 }
416
udphy_dplane_enable(struct rockchip_udphy * udphy,int dp_lanes)417 static int udphy_dplane_enable(struct rockchip_udphy *udphy, int dp_lanes)
418 {
419 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
420 int ret = 0;
421
422 if (cfg->dplane_enable)
423 ret = cfg->dplane_enable(udphy, dp_lanes);
424
425 return ret;
426 }
427
upphy_set_typec_default_mapping(struct rockchip_udphy * udphy)428 static int upphy_set_typec_default_mapping(struct rockchip_udphy *udphy)
429 {
430 if (udphy->flip) {
431 udphy->dp_lane_sel[0] = 0;
432 udphy->dp_lane_sel[1] = 1;
433 udphy->dp_lane_sel[2] = 3;
434 udphy->dp_lane_sel[3] = 2;
435 udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP;
436 udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP;
437 udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB;
438 udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB;
439 udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_INVERT;
440 udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_INVERT;
441 gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 1);
442 gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 0);
443 } else {
444 udphy->dp_lane_sel[0] = 2;
445 udphy->dp_lane_sel[1] = 3;
446 udphy->dp_lane_sel[2] = 1;
447 udphy->dp_lane_sel[3] = 0;
448 udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB;
449 udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB;
450 udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP;
451 udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP;
452 udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_NORMAL;
453 udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_NORMAL;
454 gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 0);
455 gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 1);
456 }
457
458 udphy->mode = UDPHY_MODE_DP_USB;
459
460 return 0;
461 }
462
udphy_orien_sw_set(struct typec_switch * sw,enum typec_orientation orien)463 static int udphy_orien_sw_set(struct typec_switch *sw,
464 enum typec_orientation orien)
465 {
466 struct rockchip_udphy *udphy = typec_switch_get_drvdata(sw);
467
468 mutex_lock(&udphy->mutex);
469
470 if (orien == TYPEC_ORIENTATION_NONE) {
471 gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 0);
472 gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 0);
473 /* unattached */
474 udphy_usb_bvalid_enable(udphy, false);
475 goto unlock_ret;
476 }
477
478 udphy->flip = (orien == TYPEC_ORIENTATION_REVERSE) ? true : false;
479 upphy_set_typec_default_mapping(udphy);
480 udphy_usb_bvalid_enable(udphy, true);
481
482 unlock_ret:
483 mutex_unlock(&udphy->mutex);
484 return 0;
485 }
486
udphy_setup_orien_switch(struct rockchip_udphy * udphy)487 static int udphy_setup_orien_switch(struct rockchip_udphy *udphy)
488 {
489 struct typec_switch_desc sw_desc = { };
490
491 sw_desc.drvdata = udphy;
492 sw_desc.fwnode = dev_fwnode(udphy->dev);
493 sw_desc.set = udphy_orien_sw_set;
494
495 udphy->sw = typec_switch_register(udphy->dev, &sw_desc);
496 if (IS_ERR(udphy->sw)) {
497 dev_err(udphy->dev, "Error register typec orientation switch: %ld\n",
498 PTR_ERR(udphy->sw));
499 return PTR_ERR(udphy->sw);
500 }
501
502 return 0;
503 }
504
udphy_orien_switch_unregister(void * data)505 static void udphy_orien_switch_unregister(void *data)
506 {
507 struct rockchip_udphy *udphy = data;
508
509 typec_switch_unregister(udphy->sw);
510 }
511
udphy_setup(struct rockchip_udphy * udphy)512 static int udphy_setup(struct rockchip_udphy *udphy)
513 {
514 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
515 int ret = 0;
516
517 mutex_lock(&udphy->mutex);
518
519 ret = clk_bulk_prepare_enable(udphy->num_clks, udphy->clks);
520 if (ret) {
521 dev_err(udphy->dev, "failed to enable clk\n");
522 goto unlock;
523 }
524
525 if (cfg->combophy_init) {
526 ret = cfg->combophy_init(udphy);
527 if (ret) {
528 dev_err(udphy->dev, "failed to init combophy\n");
529 goto disable_clks;
530 }
531 }
532
533 mutex_unlock(&udphy->mutex);
534 return 0;
535
536 disable_clks:
537 clk_bulk_disable_unprepare(udphy->num_clks, udphy->clks);
538 unlock:
539 mutex_unlock(&udphy->mutex);
540 return ret;
541 }
542
udphy_disable(struct rockchip_udphy * udphy)543 static int udphy_disable(struct rockchip_udphy *udphy)
544 {
545 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
546 int i;
547
548 mutex_lock(&udphy->mutex);
549
550 clk_bulk_disable_unprepare(udphy->num_clks, udphy->clks);
551
552 for (i = 0; i < cfg->num_rsts; i++)
553 reset_control_assert(udphy->rsts[i]);
554
555 mutex_unlock(&udphy->mutex);
556 return 0;
557 }
558
udphy_parse_lane_mux_data(struct rockchip_udphy * udphy,struct device_node * np)559 static int udphy_parse_lane_mux_data(struct rockchip_udphy *udphy, struct device_node *np)
560 {
561 struct property *prop;
562 int ret, i, len, num_lanes;
563
564 prop = of_find_property(np, "rockchip,dp-lane-mux", &len);
565 if (!prop) {
566 dev_dbg(udphy->dev, "failed to find dp lane mux, following dp alt mode\n");
567 udphy->mode = UDPHY_MODE_USB;
568 return 0;
569 }
570
571 num_lanes = len / sizeof(u32);
572
573 if (num_lanes != 2 && num_lanes != 4) {
574 dev_err(udphy->dev, "invalid number of lane mux\n");
575 return -EINVAL;
576 }
577
578 ret = of_property_read_u32_array(np, "rockchip,dp-lane-mux", udphy->dp_lane_sel, num_lanes);
579 if (ret) {
580 dev_err(udphy->dev, "get dp lane mux failed\n");
581 return -EINVAL;
582 }
583
584 for (i = 0; i < num_lanes; i++) {
585 int j;
586
587 if (udphy->dp_lane_sel[i] > 3) {
588 dev_err(udphy->dev, "lane mux between 0 and 3, exceeding the range\n");
589 return -EINVAL;
590 }
591
592 udphy->lane_mux_sel[udphy->dp_lane_sel[i]] = PHY_LANE_MUX_DP;
593
594 for (j = i + 1; j < num_lanes; j++) {
595 if (udphy->dp_lane_sel[i] == udphy->dp_lane_sel[j]) {
596 dev_err(udphy->dev, "set repeat lane mux value\n");
597 return -EINVAL;
598 }
599 }
600 }
601
602 udphy->mode = UDPHY_MODE_DP;
603 if (num_lanes == 2)
604 udphy->mode |= UDPHY_MODE_USB;
605
606 return 0;
607 }
608
udphy_parse_dt(struct rockchip_udphy * udphy,struct device * dev)609 static int udphy_parse_dt(struct rockchip_udphy *udphy, struct device *dev)
610 {
611 struct device_node *np = dev->of_node;
612 enum usb_device_speed maximum_speed;
613 int ret;
614
615 udphy->u2phygrf = syscon_regmap_lookup_by_phandle(np, "rockchip,u2phy-grf");
616 if (IS_ERR(udphy->u2phygrf)) {
617 if (PTR_ERR(udphy->u2phygrf) == -ENODEV) {
618 dev_warn(dev, "missing u2phy-grf dt node\n");
619 udphy->u2phygrf = NULL;
620 } else {
621 return PTR_ERR(udphy->u2phygrf);
622 }
623 }
624
625 udphy->udphygrf = syscon_regmap_lookup_by_phandle(np, "rockchip,usbdpphy-grf");
626 if (IS_ERR(udphy->udphygrf)) {
627 if (PTR_ERR(udphy->udphygrf) == -ENODEV) {
628 dev_warn(dev, "missing usbdpphy-grf dt node\n");
629 udphy->udphygrf = NULL;
630 } else {
631 return PTR_ERR(udphy->udphygrf);
632 }
633 }
634
635 udphy->usbgrf = syscon_regmap_lookup_by_phandle(np, "rockchip,usb-grf");
636 if (IS_ERR(udphy->usbgrf)) {
637 if (PTR_ERR(udphy->usbgrf) == -ENODEV) {
638 dev_warn(dev, "missing usb-grf dt node\n");
639 udphy->usbgrf = NULL;
640 } else {
641 return PTR_ERR(udphy->usbgrf);
642 }
643 }
644
645 udphy->vogrf = syscon_regmap_lookup_by_phandle(np, "rockchip,vo-grf");
646 if (IS_ERR(udphy->vogrf)) {
647 if (PTR_ERR(udphy->vogrf) == -ENODEV) {
648 dev_warn(dev, "missing vo-grf dt node\n");
649 udphy->vogrf = NULL;
650 } else {
651 return PTR_ERR(udphy->vogrf);
652 }
653 }
654
655 ret = udphy_parse_lane_mux_data(udphy, np);
656 if (ret)
657 return ret;
658
659 udphy->sbu1_dc_gpio = devm_gpiod_get_optional(dev, "sbu1-dc", GPIOD_OUT_LOW);
660 if (IS_ERR(udphy->sbu1_dc_gpio))
661 return PTR_ERR(udphy->sbu1_dc_gpio);
662
663 udphy->sbu2_dc_gpio = devm_gpiod_get_optional(dev, "sbu2-dc", GPIOD_OUT_LOW);
664 if (IS_ERR(udphy->sbu2_dc_gpio))
665 return PTR_ERR(udphy->sbu2_dc_gpio);
666
667 if (device_property_present(dev, "maximum-speed")) {
668 maximum_speed = usb_get_maximum_speed(dev);
669 udphy->hs = maximum_speed <= USB_SPEED_HIGH ? true : false;
670 }
671
672 ret = udphy_clk_init(udphy, dev);
673 if (ret)
674 return ret;
675
676 ret = udphy_reset_init(udphy, dev);
677 if (ret)
678 return ret;
679
680 return 0;
681 }
682
udphy_power_on(struct rockchip_udphy * udphy,u8 mode)683 static int udphy_power_on(struct rockchip_udphy *udphy, u8 mode)
684 {
685 int ret;
686
687 if (!(udphy->mode & mode)) {
688 dev_info(udphy->dev, "mode 0x%02x is not support\n", mode);
689 return 0;
690 }
691
692 if (udphy->status == UDPHY_MODE_NONE) {
693 udphy->mode_change = false;
694 ret = udphy_setup(udphy);
695 if (ret)
696 return ret;
697
698 if (udphy->mode & UDPHY_MODE_USB)
699 udphy_u3_port_disable(udphy, false);
700 } else if (udphy->mode_change) {
701 udphy->mode_change = false;
702 udphy->status = UDPHY_MODE_NONE;
703 if (udphy->mode == UDPHY_MODE_DP)
704 udphy_u3_port_disable(udphy, true);
705
706 ret = udphy_disable(udphy);
707 if (ret)
708 return ret;
709 ret = udphy_setup(udphy);
710 if (ret)
711 return ret;
712 }
713
714 udphy->status |= mode;
715
716 return 0;
717 }
718
udphy_power_off(struct rockchip_udphy * udphy,u8 mode)719 static int udphy_power_off(struct rockchip_udphy *udphy, u8 mode)
720 {
721 int ret;
722
723 if (!(udphy->mode & mode)) {
724 dev_info(udphy->dev, "mode 0x%02x is not support\n", mode);
725 return 0;
726 }
727
728 if (!udphy->status)
729 return 0;
730
731 udphy->status &= ~mode;
732
733 if (udphy->status == UDPHY_MODE_NONE) {
734 ret = udphy_disable(udphy);
735 if (ret)
736 return ret;
737 }
738
739 return 0;
740 }
741
rockchip_dp_phy_power_on(struct phy * phy)742 static int rockchip_dp_phy_power_on(struct phy *phy)
743 {
744 struct rockchip_udphy *udphy = phy_get_drvdata(phy);
745 int ret, dp_lanes;
746
747 dp_lanes = udphy_dplane_get(udphy);
748 phy_set_bus_width(phy, dp_lanes);
749
750 ret = udphy_power_on(udphy, UDPHY_MODE_DP);
751 if (ret)
752 return ret;
753
754 ret = udphy_dplane_enable(udphy, dp_lanes);
755 if (ret)
756 return ret;
757
758 return udphy_dplane_select(udphy);
759
760 }
761
rockchip_dp_phy_power_off(struct phy * phy)762 static int rockchip_dp_phy_power_off(struct phy *phy)
763 {
764 struct rockchip_udphy *udphy = phy_get_drvdata(phy);
765 int ret;
766
767 ret = udphy_dplane_enable(udphy, 0);
768 if (ret)
769 return ret;
770
771 return udphy_power_off(udphy, UDPHY_MODE_DP);
772 }
773
rockchip_dp_phy_verify_config(struct rockchip_udphy * udphy,struct phy_configure_opts_dp * dp)774 static int rockchip_dp_phy_verify_config(struct rockchip_udphy *udphy,
775 struct phy_configure_opts_dp *dp)
776 {
777 int i;
778
779 /* If changing link rate was required, verify it's supported. */
780 if (dp->set_rate) {
781 switch (dp->link_rate) {
782 case 1620:
783 case 2700:
784 case 5400:
785 case 8100:
786 /* valid bit rate */
787 break;
788 default:
789 return -EINVAL;
790 }
791 }
792
793 /* Verify lane count. */
794 switch (dp->lanes) {
795 case 1:
796 case 2:
797 case 4:
798 /* valid lane count. */
799 break;
800 default:
801 return -EINVAL;
802 }
803
804 /*
805 * If changing voltages is required, check swing and pre-emphasis
806 * levels, per-lane.
807 */
808 if (dp->set_voltages) {
809 /* Lane count verified previously. */
810 for (i = 0; i < dp->lanes; i++) {
811 if (dp->voltage[i] > 3 || dp->pre[i] > 3)
812 return -EINVAL;
813
814 /*
815 * Sum of voltage swing and pre-emphasis levels cannot
816 * exceed 3.
817 */
818 if (dp->voltage[i] + dp->pre[i] > 3)
819 return -EINVAL;
820 }
821 }
822
823 return 0;
824 }
825
rockchip_dp_phy_configure(struct phy * phy,union phy_configure_opts * opts)826 static int rockchip_dp_phy_configure(struct phy *phy,
827 union phy_configure_opts *opts)
828 {
829 struct rockchip_udphy *udphy = phy_get_drvdata(phy);
830 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
831 int ret;
832
833 ret = rockchip_dp_phy_verify_config(udphy, &opts->dp);
834 if (ret)
835 return ret;
836
837 if (opts->dp.set_rate && cfg->dp_phy_set_rate) {
838 ret = cfg->dp_phy_set_rate(udphy, &opts->dp);
839 if (ret) {
840 dev_err(udphy->dev,
841 "rockchip_hdptx_phy_set_rate failed\n");
842 return ret;
843 }
844 }
845
846 if (opts->dp.set_voltages && cfg->dp_phy_set_voltages) {
847 ret = cfg->dp_phy_set_voltages(udphy, &opts->dp);
848 if (ret) {
849 dev_err(udphy->dev,
850 "rockchip_dp_phy_set_voltages failed\n");
851 return ret;
852 }
853 }
854
855 return 0;
856 }
857
858 static const struct phy_ops rockchip_dp_phy_ops = {
859 .power_on = rockchip_dp_phy_power_on,
860 .power_off = rockchip_dp_phy_power_off,
861 .configure = rockchip_dp_phy_configure,
862 .owner = THIS_MODULE,
863 };
864
rockchip_u3phy_init(struct phy * phy)865 static int rockchip_u3phy_init(struct phy *phy)
866 {
867 struct rockchip_udphy *udphy = phy_get_drvdata(phy);
868
869 /* DP only or high-speed, disable U3 port */
870 if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) {
871 udphy_u3_port_disable(udphy, true);
872 return 0;
873 }
874
875 return udphy_power_on(udphy, UDPHY_MODE_USB);
876 }
877
rockchip_u3phy_exit(struct phy * phy)878 static int rockchip_u3phy_exit(struct phy *phy)
879 {
880 struct rockchip_udphy *udphy = phy_get_drvdata(phy);
881
882 /* DP only or high-speed */
883 if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs)
884 return 0;
885
886 return udphy_power_off(udphy, UDPHY_MODE_USB);
887 }
888
889 static const struct phy_ops rockchip_u3phy_ops = {
890 .init = rockchip_u3phy_init,
891 .exit = rockchip_u3phy_exit,
892 .owner = THIS_MODULE,
893 };
894
usbdp_typec_mux_set(struct typec_mux * mux,struct typec_mux_state * state)895 static int usbdp_typec_mux_set(struct typec_mux *mux,
896 struct typec_mux_state *state)
897 {
898 struct rockchip_udphy *udphy = typec_mux_get_drvdata(mux);
899 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
900 u8 mode;
901
902 switch (state->mode) {
903 case TYPEC_DP_STATE_C:
904 fallthrough;
905 case TYPEC_DP_STATE_E:
906 udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP;
907 udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP;
908 udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP;
909 udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP;
910 mode = UDPHY_MODE_DP;
911 break;
912 case TYPEC_DP_STATE_D:
913 fallthrough;
914 default:
915 if (udphy->flip) {
916 udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP;
917 udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP;
918 udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB;
919 udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB;
920 } else {
921 udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB;
922 udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB;
923 udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP;
924 udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP;
925 }
926 mode = UDPHY_MODE_DP_USB;
927 break;
928 }
929
930 if (state->alt && state->alt->svid == USB_TYPEC_DP_SID) {
931 struct typec_displayport_data *data = state->data;
932 bool hpd = !!(data && (data->status & DP_STATUS_HPD_STATE));
933
934 if (hpd && udphy->mode != mode) {
935 udphy->mode = mode;
936 udphy->mode_change = true;
937 }
938
939 if (cfg->hpd_event_trigger)
940 cfg->hpd_event_trigger(udphy, hpd);
941 }
942
943 return 0;
944 }
945
udphy_setup_typec_mux(struct rockchip_udphy * udphy)946 static int udphy_setup_typec_mux(struct rockchip_udphy *udphy)
947 {
948 struct typec_mux_desc mux_desc = {};
949
950 mux_desc.drvdata = udphy;
951 mux_desc.fwnode = dev_fwnode(udphy->dev);
952 mux_desc.set = usbdp_typec_mux_set;
953
954 udphy->mux = typec_mux_register(udphy->dev, &mux_desc);
955 if (IS_ERR(udphy->mux)) {
956 dev_err(udphy->dev, "Error register typec mux: %ld\n",
957 PTR_ERR(udphy->mux));
958 return PTR_ERR(udphy->mux);
959 }
960
961 return 0;
962 }
963
udphy_typec_mux_unregister(void * data)964 static void udphy_typec_mux_unregister(void *data)
965 {
966 struct rockchip_udphy *udphy = data;
967
968 typec_mux_unregister(udphy->mux);
969 }
970
971 static const struct regmap_config rockchip_udphy_pma_regmap_cfg = {
972 .reg_bits = 32,
973 .reg_stride = 4,
974 .val_bits = 32,
975 .fast_io = true,
976 .max_register = 0x20dc,
977 };
978
rockchip_udphy_probe(struct platform_device * pdev)979 static int rockchip_udphy_probe(struct platform_device *pdev)
980 {
981 struct device *dev = &pdev->dev;
982 struct device_node *np = dev->of_node;
983 struct device_node *child_np;
984 struct phy_provider *phy_provider;
985 struct resource *res;
986 struct rockchip_udphy *udphy;
987 const struct rockchip_udphy_cfg *phy_cfgs;
988 void __iomem *base;
989 int id, ret;
990
991 udphy = devm_kzalloc(dev, sizeof(*udphy), GFP_KERNEL);
992 if (!udphy)
993 return -ENOMEM;
994
995 id = of_alias_get_id(dev->of_node, "usbdp");
996 if (id < 0)
997 id = 0;
998 udphy->id = id;
999
1000 phy_cfgs = of_device_get_match_data(dev);
1001 if (!phy_cfgs) {
1002 dev_err(dev, "no OF data can be matched with %p node\n", np);
1003 return -EINVAL;
1004 }
1005
1006 udphy->cfgs = phy_cfgs;
1007
1008 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1009 base = devm_ioremap_resource(dev, res);
1010 if (IS_ERR(base))
1011 return PTR_ERR(base);
1012
1013 udphy->pma_regmap = devm_regmap_init_mmio(dev, base + UDPHY_PMA,
1014 &rockchip_udphy_pma_regmap_cfg);
1015 if (IS_ERR(udphy->pma_regmap))
1016 return PTR_ERR(udphy->pma_regmap);
1017
1018 ret = udphy_parse_dt(udphy, dev);
1019 if (ret)
1020 return ret;
1021
1022 mutex_init(&udphy->mutex);
1023 udphy->dev = dev;
1024 platform_set_drvdata(pdev, udphy);
1025
1026 if (device_property_present(dev, "orientation-switch")) {
1027 ret = udphy_setup_orien_switch(udphy);
1028 if (ret)
1029 return ret;
1030
1031 ret = devm_add_action_or_reset(dev, udphy_orien_switch_unregister, udphy);
1032 if (ret)
1033 return ret;
1034 }
1035
1036 ret = udphy_setup_typec_mux(udphy);
1037 if (ret)
1038 return ret;
1039
1040 ret = devm_add_action_or_reset(dev, udphy_typec_mux_unregister, udphy);
1041 if (ret)
1042 return ret;
1043
1044 for_each_available_child_of_node(np, child_np) {
1045 struct phy *phy;
1046
1047 if (of_node_name_eq(child_np, "dp-port"))
1048 phy = devm_phy_create(dev, child_np, &rockchip_dp_phy_ops);
1049 else if (of_node_name_eq(child_np, "u3-port"))
1050 phy = devm_phy_create(dev, child_np, &rockchip_u3phy_ops);
1051 else
1052 continue;
1053
1054 if (IS_ERR(phy)) {
1055 dev_err(dev, "failed to create phy: %pOFn\n", child_np);
1056 goto put_child;
1057 }
1058
1059 phy_set_drvdata(phy, udphy);
1060 }
1061
1062 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1063 if (IS_ERR(phy_provider)) {
1064 dev_err(dev, "failed to register phy provider\n");
1065 goto put_child;
1066 }
1067
1068 return 0;
1069
1070 put_child:
1071 of_node_put(child_np);
1072 return ret;
1073 }
1074
rk3588_udphy_refclk_set(struct rockchip_udphy * udphy)1075 static int rk3588_udphy_refclk_set(struct rockchip_udphy *udphy)
1076 {
1077 unsigned long rate;
1078 int ret;
1079
1080 /* configure phy reference clock */
1081 rate = clk_get_rate(udphy->refclk);
1082 dev_dbg(udphy->dev, "refclk freq %ld\n", rate);
1083
1084 switch (rate) {
1085 case 24000000:
1086 ret = regmap_multi_reg_write(udphy->pma_regmap, rk3588_udphy_24m_refclk_cfg,
1087 ARRAY_SIZE(rk3588_udphy_24m_refclk_cfg));
1088 if (ret)
1089 return ret;
1090 break;
1091 case 26000000:
1092 /* register default is 26MHz */
1093 ret = regmap_multi_reg_write(udphy->pma_regmap, rk3588_udphy_26m_refclk_cfg,
1094 ARRAY_SIZE(rk3588_udphy_26m_refclk_cfg));
1095 if (ret)
1096 return ret;
1097 break;
1098 default:
1099 dev_err(udphy->dev, "unsupported refclk freq %ld\n", rate);
1100 return -EINVAL;
1101 }
1102
1103 return 0;
1104 }
1105
rk3588_udphy_status_check(struct rockchip_udphy * udphy)1106 static int rk3588_udphy_status_check(struct rockchip_udphy *udphy)
1107 {
1108 unsigned int val;
1109 int ret;
1110
1111 /* LCPLL check */
1112 if (udphy->mode & UDPHY_MODE_USB) {
1113 ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_LCPLL_DONE_OFFSET,
1114 val, (val & CMN_ANA_LCPLL_AFC_DONE) &&
1115 (val & CMN_ANA_LCPLL_LOCK_DONE), 200, 100000);
1116 if (ret) {
1117 dev_err(udphy->dev, "cmn ana lcpll lock timeout\n");
1118 return ret;
1119 }
1120 }
1121
1122 if (udphy->mode & UDPHY_MODE_USB) {
1123 if (!udphy->flip) {
1124 ret = regmap_read_poll_timeout(udphy->pma_regmap,
1125 TRSV_LN0_MON_RX_CDR_DONE_OFFSET, val,
1126 val & TRSV_LN0_MON_RX_CDR_LOCK_DONE,
1127 200, 100000);
1128 if (ret)
1129 dev_err(udphy->dev, "trsv ln0 mon rx cdr lock timeout\n");
1130 } else {
1131 ret = regmap_read_poll_timeout(udphy->pma_regmap,
1132 TRSV_LN2_MON_RX_CDR_DONE_OFFSET, val,
1133 val & TRSV_LN2_MON_RX_CDR_LOCK_DONE,
1134 200, 100000);
1135 if (ret)
1136 dev_err(udphy->dev, "trsv ln2 mon rx cdr lock timeout\n");
1137 }
1138 }
1139
1140 return 0;
1141 }
1142
rk3588_udphy_init(struct rockchip_udphy * udphy)1143 static int rk3588_udphy_init(struct rockchip_udphy *udphy)
1144 {
1145 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
1146 int ret;
1147
1148 /* enable rx lfps for usb */
1149 if (udphy->mode & UDPHY_MODE_USB)
1150 grfreg_write(udphy->udphygrf, &cfg->grfcfg.rx_lfps, true);
1151
1152 /* Step 1: power on pma and deassert apb rstn */
1153 grfreg_write(udphy->udphygrf, &cfg->grfcfg.low_pwrn, true);
1154
1155 udphy_reset_deassert(udphy, "pma_apb");
1156 udphy_reset_deassert(udphy, "pcs_apb");
1157
1158 /* Step 2: set init sequence and phy refclk */
1159 ret = regmap_multi_reg_write(udphy->pma_regmap, rk3588_udphy_init_sequence,
1160 ARRAY_SIZE(rk3588_udphy_init_sequence));
1161 if (ret) {
1162 dev_err(udphy->dev, "init sequence set error %d\n", ret);
1163 goto assert_apb;
1164 }
1165
1166 ret = rk3588_udphy_refclk_set(udphy);
1167 if (ret) {
1168 dev_err(udphy->dev, "refclk set error %d\n", ret);
1169 goto assert_apb;
1170 }
1171
1172 /* Step 3: configure lane mux */
1173 regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET,
1174 CMN_DP_LANE_MUX_ALL | CMN_DP_LANE_EN_ALL,
1175 FIELD_PREP(CMN_DP_LANE_MUX_N(3), udphy->lane_mux_sel[3]) |
1176 FIELD_PREP(CMN_DP_LANE_MUX_N(2), udphy->lane_mux_sel[2]) |
1177 FIELD_PREP(CMN_DP_LANE_MUX_N(1), udphy->lane_mux_sel[1]) |
1178 FIELD_PREP(CMN_DP_LANE_MUX_N(0), udphy->lane_mux_sel[0]) |
1179 FIELD_PREP(CMN_DP_LANE_EN_ALL, 0));
1180
1181 /* Step 4: deassert init rstn and wait for 200ns from datasheet */
1182 if (udphy->mode & UDPHY_MODE_USB)
1183 udphy_reset_deassert(udphy, "init");
1184
1185 if (udphy->mode & UDPHY_MODE_DP) {
1186 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET,
1187 CMN_DP_INIT_RSTN,
1188 FIELD_PREP(CMN_DP_INIT_RSTN, 0x1));
1189 }
1190
1191 udelay(1);
1192
1193 /* Step 5: deassert cmn/lane rstn */
1194 if (udphy->mode & UDPHY_MODE_USB) {
1195 udphy_reset_deassert(udphy, "cmn");
1196 udphy_reset_deassert(udphy, "lane");
1197 }
1198
1199 /* Step 6: wait for lock done of pll */
1200 ret = rk3588_udphy_status_check(udphy);
1201 if (ret)
1202 goto assert_phy;
1203
1204 return 0;
1205
1206 assert_phy:
1207 udphy_reset_assert(udphy, "init");
1208 udphy_reset_assert(udphy, "cmn");
1209 udphy_reset_assert(udphy, "lane");
1210
1211 assert_apb:
1212 udphy_reset_assert(udphy, "pma_apb");
1213 udphy_reset_assert(udphy, "pcs_apb");
1214 return ret;
1215 }
1216
rk3588_udphy_hpd_event_trigger(struct rockchip_udphy * udphy,bool hpd)1217 static int rk3588_udphy_hpd_event_trigger(struct rockchip_udphy *udphy, bool hpd)
1218 {
1219 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
1220
1221 grfreg_write(udphy->vogrf, &cfg->vogrfcfg[udphy->id].hpd_trigger, hpd);
1222
1223 return 0;
1224 }
1225
rk3588_udphy_dplane_enable(struct rockchip_udphy * udphy,int dp_lanes)1226 static int rk3588_udphy_dplane_enable(struct rockchip_udphy *udphy, int dp_lanes)
1227 {
1228 int i;
1229 u32 val = 0;
1230
1231 for (i = 0; i < dp_lanes; i++)
1232 val |= BIT(udphy->dp_lane_sel[i]);
1233
1234 regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, CMN_DP_LANE_EN_ALL,
1235 FIELD_PREP(CMN_DP_LANE_EN_ALL, val));
1236
1237 if (!dp_lanes)
1238 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET,
1239 CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0));
1240
1241 return 0;
1242 }
1243
rk3588_udphy_dplane_select(struct rockchip_udphy * udphy)1244 static int rk3588_udphy_dplane_select(struct rockchip_udphy *udphy)
1245 {
1246 u32 value = 0;
1247
1248 switch (udphy->mode) {
1249 case UDPHY_MODE_DP:
1250 value |= 2 << udphy->dp_lane_sel[2] * 2;
1251 value |= 3 << udphy->dp_lane_sel[3] * 2;
1252 fallthrough;
1253 case UDPHY_MODE_DP_USB:
1254 value |= 0 << udphy->dp_lane_sel[0] * 2;
1255 value |= 1 << udphy->dp_lane_sel[1] * 2;
1256 break;
1257 case UDPHY_MODE_USB:
1258 break;
1259 default:
1260 break;
1261 }
1262
1263 regmap_write(udphy->vogrf, udphy->id ? RK3588_GRF_VO0_CON2 : RK3588_GRF_VO0_CON0,
1264 ((DP_AUX_DIN_SEL | DP_AUX_DOUT_SEL | DP_LANE_SEL_ALL) << 16) |
1265 FIELD_PREP(DP_AUX_DIN_SEL, udphy->dp_aux_din_sel) |
1266 FIELD_PREP(DP_AUX_DOUT_SEL, udphy->dp_aux_dout_sel) | value);
1267
1268 return 0;
1269 }
1270
rk3588_dp_phy_set_rate(struct rockchip_udphy * udphy,struct phy_configure_opts_dp * dp)1271 static int rk3588_dp_phy_set_rate(struct rockchip_udphy *udphy,
1272 struct phy_configure_opts_dp *dp)
1273 {
1274 u8 bw;
1275 u32 val;
1276 int ret;
1277
1278 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET,
1279 CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0));
1280
1281 switch (dp->link_rate) {
1282 case 1620:
1283 bw = DP_BW_RBR;
1284 break;
1285 case 2700:
1286 bw = DP_BW_HBR;
1287 break;
1288 case 5400:
1289 bw = DP_BW_HBR2;
1290 break;
1291 case 8100:
1292 bw = DP_BW_HBR3;
1293 break;
1294 default:
1295 return -EINVAL;
1296 }
1297
1298 regmap_update_bits(udphy->pma_regmap, CMN_DP_LINK_OFFSET, CMN_DP_TX_LINK_BW,
1299 FIELD_PREP(CMN_DP_TX_LINK_BW, bw));
1300 regmap_update_bits(udphy->pma_regmap, CMN_SSC_EN_OFFSET, CMN_ROPLL_SSC_EN,
1301 FIELD_PREP(CMN_ROPLL_SSC_EN, dp->ssc));
1302 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, CMN_DP_CMN_RSTN,
1303 FIELD_PREP(CMN_DP_CMN_RSTN, 0x1));
1304
1305 ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_ROPLL_DONE_OFFSET, val,
1306 FIELD_GET(CMN_ANA_ROPLL_LOCK_DONE, val) &&
1307 FIELD_GET(CMN_ANA_ROPLL_AFC_DONE, val),
1308 0, 1000);
1309 if (ret) {
1310 dev_err(udphy->dev, "ROPLL is not lock\n");
1311 return ret;
1312 }
1313
1314 return 0;
1315 }
1316
1317 static const struct {
1318 u32 trsv_reg0204;
1319 u32 trsv_reg0205;
1320 u32 trsv_reg0206;
1321 u32 trsv_reg0207;
1322 } training_table[4][4] = {
1323 /* voltage swing 0, pre-emphasis 0->3 */
1324 {
1325 { 0x21, 0x10, 0x42, 0xe5 },
1326 { 0x25, 0x14, 0x42, 0xe5 },
1327 { 0x26, 0x17, 0x43, 0xe5 },
1328 { 0x2b, 0x1c, 0x43, 0xe7 }
1329 },
1330
1331 /* voltage swing 1, pre-emphasis 0->2 */
1332 {
1333 { 0x26, 0x10, 0x42, 0xe7 },
1334 { 0x2b, 0x15, 0x42, 0xe7 },
1335 { 0x2b, 0x18, 0x43, 0xe7 }
1336 },
1337
1338 /* voltage swing 2, pre-emphasis 0->1 */
1339 {
1340 { 0x2a, 0x10, 0x42, 0xe7 },
1341 { 0x2b, 0x15, 0x43, 0xe7 }
1342 },
1343
1344 /* voltage swing 3, pre-emphasis 0 */
1345 {
1346 { 0x2b, 0x10, 0x43, 0xe7 },
1347 },
1348 };
1349
rk3588_dp_phy_set_voltage(struct rockchip_udphy * udphy,u32 voltage,u32 pre,u32 lane)1350 static void rk3588_dp_phy_set_voltage(struct rockchip_udphy *udphy,
1351 u32 voltage, u32 pre, u32 lane)
1352 {
1353 u32 offset = 0x800 * lane;
1354 u32 val;
1355
1356 val = training_table[voltage][pre].trsv_reg0204;
1357 regmap_write(udphy->pma_regmap, 0x0810 + offset, val);
1358
1359 val = training_table[voltage][pre].trsv_reg0205;
1360 regmap_write(udphy->pma_regmap, 0x0814 + offset, val);
1361
1362 val = training_table[voltage][pre].trsv_reg0206;
1363 regmap_write(udphy->pma_regmap, 0x0818 + offset, val);
1364
1365 val = training_table[voltage][pre].trsv_reg0207;
1366 regmap_write(udphy->pma_regmap, 0x081c + offset, val);
1367 }
1368
rk3588_dp_phy_set_voltages(struct rockchip_udphy * udphy,struct phy_configure_opts_dp * dp)1369 static int rk3588_dp_phy_set_voltages(struct rockchip_udphy *udphy,
1370 struct phy_configure_opts_dp *dp)
1371 {
1372 u32 i, lane;
1373
1374 for (i = 0; i < dp->lanes; i++) {
1375 lane = udphy->dp_lane_sel[i];
1376 switch (dp->link_rate) {
1377 case 1620:
1378 case 2700:
1379 regmap_update_bits(udphy->pma_regmap, TRSV_ANA_TX_CLK_OFFSET_N(lane),
1380 LN_ANA_TX_SER_TXCLK_INV,
1381 FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV,
1382 udphy->lane_mux_sel[lane]));
1383 break;
1384 case 5400:
1385 case 8100:
1386 regmap_update_bits(udphy->pma_regmap, TRSV_ANA_TX_CLK_OFFSET_N(lane),
1387 LN_ANA_TX_SER_TXCLK_INV,
1388 FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV, 0x0));
1389 break;
1390 }
1391
1392 rk3588_dp_phy_set_voltage(udphy, dp->voltage[i],
1393 dp->pre[i], lane);
1394 }
1395
1396 return 0;
1397 }
1398
1399 static const char * const rk3588_udphy_rst_l[] = {
1400 "init", "cmn", "lane", "pcs_apb", "pma_apb"
1401 };
1402
1403 static const struct rockchip_udphy_cfg rk3588_udphy_cfgs = {
1404 .num_rsts = ARRAY_SIZE(rk3588_udphy_rst_l),
1405 .rst_list = rk3588_udphy_rst_l,
1406 .grfcfg = {
1407 /* u2phy-grf */
1408 .bvalid_phy_con = { 0x0008, 1, 0, 0x2, 0x3 },
1409 .bvalid_grf_con = { 0x0010, 3, 2, 0x2, 0x3 },
1410
1411 /* usb-grf */
1412 .usb3otg0_cfg = { 0x001c, 15, 0, 0x1100, 0x0188 },
1413 .usb3otg1_cfg = { 0x0034, 15, 0, 0x1100, 0x0188 },
1414
1415 /* usbdpphy-grf */
1416 .low_pwrn = { 0x0004, 13, 13, 0, 1 },
1417 .rx_lfps = { 0x0004, 14, 14, 0, 1 },
1418 },
1419 .vogrfcfg = {
1420 {
1421 .hpd_trigger = { 0x0000, 11, 10, 1, 3 },
1422 },
1423 {
1424 .hpd_trigger = { 0x0008, 11, 10, 1, 3 },
1425 },
1426 },
1427 .combophy_init = rk3588_udphy_init,
1428 .dp_phy_set_rate = rk3588_dp_phy_set_rate,
1429 .dp_phy_set_voltages = rk3588_dp_phy_set_voltages,
1430 .hpd_event_trigger = rk3588_udphy_hpd_event_trigger,
1431 .dplane_enable = rk3588_udphy_dplane_enable,
1432 .dplane_select = rk3588_udphy_dplane_select,
1433 };
1434
1435 static const struct of_device_id rockchip_udphy_dt_match[] = {
1436 {
1437 .compatible = "rockchip,rk3588-usbdp-phy",
1438 .data = &rk3588_udphy_cfgs
1439 },
1440 { /* sentinel */ }
1441 };
1442
1443 MODULE_DEVICE_TABLE(of, rockchip_udphy_dt_match);
1444
1445 static struct platform_driver rockchip_udphy_driver = {
1446 .probe = rockchip_udphy_probe,
1447 .driver = {
1448 .name = "rockchip-usbdp-phy",
1449 .of_match_table = rockchip_udphy_dt_match,
1450 },
1451 };
1452
1453 module_platform_driver(rockchip_udphy_driver);
1454
1455 MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
1456 MODULE_AUTHOR("Zhang Yubing <yubing.zhang@rock-chips.com>");
1457 MODULE_DESCRIPTION("Rockchip USBDP Combo PHY driver");
1458 MODULE_LICENSE("GPL v2");
1459