1 /* 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef I2C_HI35XX_H 17 #define I2C_HI35XX_H 18 19 20 #ifdef __cplusplus 21 #if __cplusplus 22 extern "C" { 23 #endif /* __cplusplus */ 24 #endif /* __cplusplus */ 25 26 /* 27 * I2C Registers offsets 28 */ 29 #define HI35XX_I2C_GLB 0x0 30 #define HI35XX_I2C_SCL_H 0x4 31 #define HI35XX_I2C_SCL_L 0x8 32 #define HI35XX_I2C_DATA1 0x10 33 #define HI35XX_I2C_TXF 0x20 34 #define HI35XX_I2C_RXF 0x24 35 #define HI35XX_I2C_CMD_BASE 0x30 36 #define HI35XX_I2C_LOOP1 0xb0 37 #define HI35XX_I2C_DST1 0xb4 38 #define HI35XX_I2C_TX_WATER 0xc8 39 #define HI35XX_I2C_RX_WATER 0xcc 40 #define HI35XX_I2C_CTRL1 0xd0 41 #define HI35XX_I2C_CTRL2 0xd4 42 #define HI35XX_I2C_STAT 0xd8 43 #define HI35XX_I2C_INTR_RAW 0xe0 44 #define HI35XX_I2C_INTR_EN 0xe4 45 #define HI35XX_I2C_INTR_STAT 0xe8 46 47 #ifndef BIT 48 #define BIT(n) (1U << (n)) 49 #endif 50 /* 51 * I2C Global Config Register -- HI35XX_I2C_GLB 52 * */ 53 #define GLB_EN_MASK BIT(0) 54 #define GLB_SDA_HOLD_MASK 0xffff00 55 #define GLB_SDA_HOLD_SHIFT 8 56 57 /* 58 * I2C Timing CMD Register -- HI35XX_I2C_CMD_BASE + n * 4 (n = 0, 1, 2, ... 31) 59 */ 60 #define CMD_EXIT 0x0 61 #define CMD_TX_S 0x1 62 #define CMD_TX_D1_2 0x4 63 #define CMD_TX_D1_1 0x5 64 #define CMD_TX_FIFO 0x9 65 #define CMD_RX_FIFO 0x12 66 #define CMD_RX_ACK 0x13 67 #define CMD_IGN_ACK 0x15 68 #define CMD_TX_ACK 0x16 69 #define CMD_TX_NACK 0x17 70 #define CMD_JMP1 0x18 71 #define CMD_UP_TXF 0x1d 72 #define CMD_TX_RS 0x1e 73 #define CMD_TX_P 0x1f 74 75 /* 76 * I2C Control Register 1 -- HI35XX_I2C_CTRL1 77 */ 78 #define CTRL1_CMD_START_MASK BIT(0) 79 #define CTRL1_DMA_MASK (BIT(9) | BIT(8)) 80 #define CTRL1_DMA_R (BIT(9) | BIT(8)) 81 #define CTRL1_DMA_W (BIT(9)) 82 83 /* 84 * I2C Status Register -- HI35XX_I2C_STAT 85 */ 86 #define STAT_RXF_NOE_MASK BIT(16) /* RX FIFO not empty flag */ 87 #define STAT_TXF_NOF_MASK BIT(19) /* TX FIFO not full flag */ 88 89 /* 90 * I2C Interrupt status and mask Register -- 91 * HI35XX_I2C_INTR_RAW, HI35XX_I2C_STAT, HI35XX_I2C_INTR_STAT 92 */ 93 #define INTR_ABORT_MASK (BIT(0) | BIT(11)) 94 #define INTR_RX_MASK BIT(2) 95 #define INTR_TX_MASK BIT(4) 96 #define INTR_CMD_DONE_MASK BIT(12) 97 #define INTR_USE_MASK (INTR_ABORT_MASK \ 98 |INTR_RX_MASK \ 99 | INTR_TX_MASK \ 100 | INTR_CMD_DONE_MASK) 101 #define INTR_ALL_MASK 0xffffffff 102 103 #define I2C_DEFAULT_FREQUENCY 100000 104 #define I2C_TXF_DEPTH 64 105 #define I2C_RXF_DEPTH 64 106 #define I2C_TXF_WATER 32 107 #define I2C_RXF_WATER 32 108 #define I2C_WAIT_TIMEOUT 0x800 109 #define I2C_TIMEOUT_COUNT 0x10000 110 #define I2C_IRQ_TIMEOUT (msecs_to_jiffies(1000)) 111 /* for i2c rescue */ 112 #define CHECK_SDA_IN_SHIFT 16 113 #define GPIO_MODE_SHIFT 8 114 #define FORCE_SCL_OEN_SHIFT 4 115 #define FORCE_SDA_OEN_SHIFT 0 116 117 #ifdef __cplusplus 118 #if __cplusplus 119 } 120 #endif /* __cplusplus */ 121 #endif /* __cplusplus */ 122 #endif /* I2C_HI35XX_H */ 123