1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * MFD core driver for Rockchip RK806
4 *
5 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
6 *
7 * Author: Xu Shengfei <xsf@rock-chips.com>
8 */
9
10 #include <linux/interrupt.h>
11 #include <linux/mfd/core.h>
12 #include <linux/mfd/rk806.h>
13 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/of_gpio.h>
16 #include <linux/spi/spi.h>
17
18 #define TSD_TEMP_140 0x00
19 #define TSD_TEMP_160 0x01
20 #define VB_LO_ACT_SD 0x00
21 #define VB_LO_ACT_INT 0x01
22
23 static const struct reg_field rk806_reg_fields[] = {
24 [POWER_EN0] = REG_FIELD(0x00, 0, 7),
25 [POWER_EN1] = REG_FIELD(0x01, 0, 7),
26 [POWER_EN2] = REG_FIELD(0x02, 0, 7),
27 [POWER_EN3] = REG_FIELD(0x03, 0, 7),
28 [POWER_EN4] = REG_FIELD(0x04, 0, 7),
29 [POWER_EN5] = REG_FIELD(0x05, 0, 7),
30
31 [BUCK4_EN_MASK] = REG_FIELD(0x00, 7, 7),
32 [BUCK3_EN_MASK] = REG_FIELD(0x00, 6, 6),
33 [BUCK2_EN_MASK] = REG_FIELD(0x00, 5, 5),
34 [BUCK1_EN_MASK] = REG_FIELD(0x00, 4, 4),
35 [BUCK4_EN] = REG_FIELD(0X00, 3, 3),
36 [BUCK3_EN] = REG_FIELD(0X00, 2, 2),
37 [BUCK2_EN] = REG_FIELD(0X00, 1, 1),
38 [BUCK1_EN] = REG_FIELD(0X00, 0, 0),
39 [BUCK8_EN_MASK] = REG_FIELD(0x01, 7, 7),
40 [BUCK7_EN_MASK] = REG_FIELD(0x01, 6, 6),
41 [BUCK6_EN_MASK] = REG_FIELD(0x01, 5, 5),
42 [BUCK5_EN_MASK] = REG_FIELD(0x01, 4, 4),
43 [BUCK8_EN] = REG_FIELD(0x01, 3, 3),
44 [BUCK7_EN] = REG_FIELD(0x01, 2, 2),
45 [BUCK6_EN] = REG_FIELD(0x01, 1, 1),
46 [BUCK5_EN] = REG_FIELD(0x01, 0, 0),
47 [BUCK10_EN_MASK] = REG_FIELD(0x02, 5, 5),
48 [BUCK9_EN_MASK] = REG_FIELD(0x02, 4, 4),
49 [BUCK10_EN] = REG_FIELD(0x02, 1, 1),
50 [BUCK9_EN] = REG_FIELD(0x02, 0, 0),
51 [NLDO4_EN_MASK] = REG_FIELD(0x03, 7, 7),
52 [NLDO3_EN_MASK] = REG_FIELD(0x03, 6, 6),
53 [NLDO2_EN_MASK] = REG_FIELD(0x03, 5, 5),
54 [NLDO1_EN_MASK] = REG_FIELD(0x03, 4, 4),
55 [NLDO4_EN] = REG_FIELD(0x03, 3, 3),
56 [NLDO3_EN] = REG_FIELD(0x03, 2, 2),
57 [NLDO2_EN] = REG_FIELD(0x03, 1, 1),
58 [NLDO1_EN] = REG_FIELD(0x03, 0, 0),
59
60 [PLDO3_EN_MASK] = REG_FIELD(0x04, 7, 7),
61 [PLDO2_EN_MASK] = REG_FIELD(0x04, 6, 6),
62 [PLDO1_EN_MASK] = REG_FIELD(0x04, 5, 5),
63 [PLDO6_EN_MASK] = REG_FIELD(0x04, 4, 4),
64 [PLDO3_EN] = REG_FIELD(0x04, 3, 3),
65 [PLDO2_EN] = REG_FIELD(0x04, 2, 2),
66 [PLDO1_EN] = REG_FIELD(0x04, 1, 1),
67 [PLDO6_EN] = REG_FIELD(0x04, 0, 0),
68
69 [NLDO5_EN_MASK] = REG_FIELD(0x05, 6, 6),
70 [PLDO5_EN_MASK] = REG_FIELD(0x05, 5, 5),
71 [PLDO4_EN_MASK] = REG_FIELD(0x05, 4, 4),
72 [NLDO5_EN] = REG_FIELD(0x05, 2, 2),
73 [PLDO5_EN] = REG_FIELD(0x05, 1, 1),
74 [PLDO4_EN] = REG_FIELD(0x05, 0, 0),
75
76 [BUCK8_SLP_EN] = REG_FIELD(0x06, 7, 7),
77 [BUCK7_SLP_EN] = REG_FIELD(0x06, 6, 6),
78 [BUCK6_SLP_EN] = REG_FIELD(0x06, 5, 5),
79 [BUCK5_SLP_EN] = REG_FIELD(0x06, 4, 4),
80 [BUCK4_SLP_EN] = REG_FIELD(0x06, 3, 3),
81 [BUCK3_SLP_EN] = REG_FIELD(0x06, 2, 2),
82 [BUCK2_SLP_EN] = REG_FIELD(0x06, 1, 1),
83 [BUCK1_SLP_EN] = REG_FIELD(0x06, 0, 0),
84
85 [BUCK10_SLP_EN] = REG_FIELD(0x07, 7, 7),
86 [BUCK9_SLP_EN] = REG_FIELD(0x07, 6, 6),
87 [NLDO5_SLP_EN] = REG_FIELD(0x07, 4, 4),
88 [NLDO4_SLP_EN] = REG_FIELD(0x07, 3, 3),
89 [NLDO3_SLP_EN] = REG_FIELD(0x07, 2, 2),
90 [NLDO2_SLP_EN] = REG_FIELD(0x07, 1, 1),
91 [NLDO1_SLP_EN] = REG_FIELD(0x07, 0, 0),
92
93 [PLDO5_SLP_EN] = REG_FIELD(0x08, 5, 5),
94 [PLDO4_SLP_EN] = REG_FIELD(0x08, 4, 4),
95 [PLDO3_SLP_EN] = REG_FIELD(0x08, 3, 3),
96 [PLDO2_SLP_EN] = REG_FIELD(0x08, 2, 2),
97 [PLDO1_SLP_EN] = REG_FIELD(0x08, 1, 1),
98 [PLDO6_SLP_EN] = REG_FIELD(0x08, 0, 0),
99
100 [BUCK1_RATE] = REG_FIELD(0x10, 6, 7),
101 [BUCK2_RATE] = REG_FIELD(0x11, 6, 7),
102 [BUCK3_RATE] = REG_FIELD(0x12, 6, 7),
103 [BUCK4_RATE] = REG_FIELD(0x13, 6, 7),
104 [BUCK5_RATE] = REG_FIELD(0x14, 6, 7),
105 [BUCK6_RATE] = REG_FIELD(0x15, 6, 7),
106 [BUCK7_RATE] = REG_FIELD(0x16, 6, 7),
107 [BUCK8_RATE] = REG_FIELD(0x17, 6, 7),
108 [BUCK9_RATE] = REG_FIELD(0x18, 6, 7),
109 [BUCK10_RATE] = REG_FIELD(0x19, 6, 7),
110
111 [BUCK1_ON_VSEL] = REG_FIELD(0x1A, 0, 7),
112 [BUCK2_ON_VSEL] = REG_FIELD(0x1B, 0, 7),
113 [BUCK3_ON_VSEL] = REG_FIELD(0x1C, 0, 7),
114 [BUCK4_ON_VSEL] = REG_FIELD(0x1D, 0, 7),
115 [BUCK5_ON_VSEL] = REG_FIELD(0x1E, 0, 7),
116 [BUCK6_ON_VSEL] = REG_FIELD(0x1F, 0, 7),
117 [BUCK7_ON_VSEL] = REG_FIELD(0x20, 0, 7),
118 [BUCK8_ON_VSEL] = REG_FIELD(0x21, 0, 7),
119 [BUCK9_ON_VSEL] = REG_FIELD(0x22, 0, 7),
120 [BUCK10_ON_VSEL] = REG_FIELD(0x23, 0, 7),
121
122 [BUCK1_SLP_VSEL] = REG_FIELD(0x24, 0, 7),
123 [BUCK2_SLP_VSEL] = REG_FIELD(0x25, 0, 7),
124 [BUCK3_SLP_VSEL] = REG_FIELD(0x26, 0, 7),
125 [BUCK4_SLP_VSEL] = REG_FIELD(0x27, 0, 7),
126 [BUCK5_SLP_VSEL] = REG_FIELD(0x28, 0, 7),
127 [BUCK6_SLP_VSEL] = REG_FIELD(0x29, 0, 7),
128 [BUCK7_SLP_VSEL] = REG_FIELD(0x2A, 0, 7),
129 [BUCK8_SLP_VSEL] = REG_FIELD(0x2B, 0, 7),
130 [BUCK9_SLP_VSEL] = REG_FIELD(0x2C, 0, 7),
131 [BUCK10_SLP_VSEL] = REG_FIELD(0x2D, 0, 7),
132
133 [NLDO1_ON_VSEL] = REG_FIELD(0x43, 0, 7),
134 [NLDO2_ON_VSEL] = REG_FIELD(0x44, 0, 7),
135 [NLDO3_ON_VSEL] = REG_FIELD(0x45, 0, 7),
136 [NLDO4_ON_VSEL] = REG_FIELD(0x46, 0, 7),
137 [NLDO5_ON_VSEL] = REG_FIELD(0x47, 0, 7),
138 [NLDO1_SLP_VSEL] = REG_FIELD(0x48, 0, 7),
139 [NLDO2_SLP_VSEL] = REG_FIELD(0x49, 0, 7),
140 [NLDO3_SLP_VSEL] = REG_FIELD(0x4A, 0, 7),
141 [NLDO4_SLP_VSEL] = REG_FIELD(0x4B, 0, 7),
142 [NLDO5_SLP_VSEL] = REG_FIELD(0x4C, 0, 7),
143
144 [PLDO1_ON_VSEL] = REG_FIELD(0x4E, 0, 7),
145 [PLDO2_ON_VSEL] = REG_FIELD(0x4F, 0, 7),
146 [PLDO3_ON_VSEL] = REG_FIELD(0x50, 0, 7),
147 [PLDO4_ON_VSEL] = REG_FIELD(0x51, 0, 7),
148 [PLDO5_ON_VSEL] = REG_FIELD(0x52, 0, 7),
149 [PLDO6_ON_VSEL] = REG_FIELD(0x53, 0, 7),
150
151 [PLDO1_SLP_VSEL] = REG_FIELD(0x54, 0, 7),
152 [PLDO2_SLP_VSEL] = REG_FIELD(0x55, 0, 7),
153 [PLDO3_SLP_VSEL] = REG_FIELD(0x56, 0, 7),
154 [PLDO4_SLP_VSEL] = REG_FIELD(0x57, 0, 7),
155 [PLDO5_SLP_VSEL] = REG_FIELD(0x58, 0, 7),
156 [PLDO6_SLP_VSEL] = REG_FIELD(0x59, 0, 7),
157
158 [CHIP_NAME_H] = REG_FIELD(0x5A, 0, 7),
159 [CHIP_NAME_L] = REG_FIELD(0x5B, 4, 7),
160 [CHIP_VER] = REG_FIELD(0x5B, 0, 3),
161 [OTP_VER] = REG_FIELD(0x5C, 0, 3),
162 /* SYS_STS */
163 [PWRON_STS] = REG_FIELD(0x5D, 7, 7),
164 [VDC_STS] = REG_FIELD(0x5D, 6, 6),
165 [VB_UV_STSS] = REG_FIELD(0x5D, 5, 5),
166 [VB_LO_STS] = REG_FIELD(0x5D, 4, 4),
167 [HOTDIE_STS] = REG_FIELD(0x5D, 3, 3),
168 [TSD_STS] = REG_FIELD(0x5D, 2, 2),
169 [VB_OV_STS] = REG_FIELD(0x5D, 0, 0),
170 /* SYS_CFG0 */
171 [VB_UV_DLY] = REG_FIELD(0x5E, 7, 7),
172 [VB_UV_SEL] = REG_FIELD(0x5E, 4, 6),
173 [VB_LO_ACT] = REG_FIELD(0x5E, 3, 3),
174 [VB_LO_SEL] = REG_FIELD(0x5E, 0, 2),
175 /* SYS_CFG1 */
176 [ABNORDET_EN] = REG_FIELD(0x5F, 7, 7),
177 [TSD_TEMP] = REG_FIELD(0x5F, 6, 6),
178 [HOTDIE_TMP] = REG_FIELD(0x5F, 4, 5),
179 [SYS_OV_SD_EN] = REG_FIELD(0x5F, 3, 3),
180 [SYS_OV_SD_DLY_SEL] = REG_FIELD(0x5F, 2, 2),
181 [DLY_ABN_SHORT] = REG_FIELD(0x5F, 0, 1),
182 /* SYS_OPTION */
183 [VCCXDET_DIS] = REG_FIELD(0x61, 4, 5),
184 [OSC_TC] = REG_FIELD(0x61, 2, 3),
185 [ENB2_2M] = REG_FIELD(0x61, 1, 1),
186 [ENB_32K] = REG_FIELD(0x61, 0, 0),
187 /* SLEEP_CONFIG0 */
188 [PWRCTRL2_POL] = REG_FIELD(0x62, 7, 7),
189 [PWRCTRL2_FUN] = REG_FIELD(0x62, 4, 6),
190 [PWRCTRL1_POL] = REG_FIELD(0x62, 3, 3),
191 [PWRCTRL1_FUN] = REG_FIELD(0x62, 0, 2),
192 /* SLEEP_CONFIG1 */
193 [PWRCTRL3_POL] = REG_FIELD(0x63, 3, 3),
194 [PWRCTRL3_FUN] = REG_FIELD(0x63, 0, 2),
195 /* SLEEP_VSEL_CTR_SEL0 */
196 [BUCK4_VSEL_CTR_SEL] = REG_FIELD(0x65, 4, 5),
197 [BUCK3_VSEL_CTR_SEL] = REG_FIELD(0x65, 0, 1),
198 [BUCK2_VSEL_CTR_SEL] = REG_FIELD(0x64, 4, 5),
199 [BUCK1_VSEL_CTR_SEL] = REG_FIELD(0x64, 0, 1),
200 /* SLEEP_VSEL_CTR_SEL1 */
201 [BUCK8_VSEL_CTR_SEL] = REG_FIELD(0x67, 4, 5),
202 [BUCK7_VSEL_CTR_SEL] = REG_FIELD(0x67, 0, 1),
203 [BUCK6_VSEL_CTR_SEL] = REG_FIELD(0x66, 4, 5),
204 [BUCK5_VSEL_CTR_SEL] = REG_FIELD(0x66, 0, 1),
205 /* SLEEP_VSEL_CTR_SEL2 */
206 [NLDO2_VSEL_CTR_SEL] = REG_FIELD(0x69, 4, 5),
207 [NLDO1_VSEL_CTR_SEL] = REG_FIELD(0x69, 0, 1),
208 [BUCK10_VSEL_CTR_SEL] = REG_FIELD(0x68, 4, 5),
209 [BUCK9_VSEL_CTR_SEL] = REG_FIELD(0x68, 0, 1),
210 /* SLEEP_VSEL_CTR_SEL3 */
211 [NLDO5_VSEL_CTR_SEL] = REG_FIELD(0x6b, 0, 1),
212 [NLDO4_VSEL_CTR_SEL] = REG_FIELD(0x6a, 4, 5),
213 [NLDO3_VSEL_CTR_SEL] = REG_FIELD(0x6a, 0, 1),
214 /* SLEEP_VSEL_CTR_SEL4 */
215 [PLDO4_VSEL_CTR_SEL] = REG_FIELD(0x6d, 4, 5),
216 [PLDO3_VSEL_CTR_SEL] = REG_FIELD(0x6d, 0, 0),
217 [PLDO2_VSEL_CTR_SEL] = REG_FIELD(0x6c, 4, 5),
218 [PLDO1_VSEL_CTR_SEL] = REG_FIELD(0x6c, 0, 1),
219 /* SLEEP_VSEL_CTR_SEL5 */
220 [PLDO6_VSEL_CTR_SEL] = REG_FIELD(0x6e, 4, 5),
221 [PLDO5_VSEL_CTR_SEL] = REG_FIELD(0x6e, 0, 1),
222 /* DVS_CTRL_SEL0 */
223 [BUCK4_DVS_CTR_SEL] = REG_FIELD(0x65, 6, 7),
224 [BUCK3_DVS_CTR_SEL] = REG_FIELD(0x65, 2, 3),
225 [BUCK2_DVS_CTR_SEL] = REG_FIELD(0x64, 6, 7),
226 [BUCK1_DVS_CTR_SEL] = REG_FIELD(0x64, 2, 3),
227 /* DVS_CTRL_SEL1*/
228 [BUCK8_DVS_CTR_SEL] = REG_FIELD(0x67, 6, 7),
229 [BUCK7_DVS_CTR_SEL] = REG_FIELD(0x67, 2, 3),
230 [BUCK6_DVS_CTR_SEL] = REG_FIELD(0x66, 6, 7),
231 [BUCK5_DVS_CTR_SEL] = REG_FIELD(0x66, 2, 3),
232 /* DVS_CTRL_SEL2 */
233 [NLDO2_DVS_CTR_SEL] = REG_FIELD(0x69, 6, 7),
234 [NLDO1_DVS_CTR_SEL] = REG_FIELD(0x69, 2, 3),
235 [BUCK10_DVS_CTR_SEL] = REG_FIELD(0x68, 6, 7),
236 [BUCK9_DVS_CTR_SEL] = REG_FIELD(0x68, 2, 3),
237 /* DVS_CTRL_SEL3 */
238 [NLDO5_DVS_CTR_SEL] = REG_FIELD(0x6b, 2, 3),
239 [NLDO4_DVS_CTR_SEL] = REG_FIELD(0x6a, 6, 7),
240 [NLDO3_DVS_CTR_SEL] = REG_FIELD(0x6a, 2, 3),
241 /* DVS_CTRL_SEL4 */
242 [PLDO4_DVS_CTR_SEL] = REG_FIELD(0x6d, 6, 7),
243 [PLDO3_DVS_CTR_SEL] = REG_FIELD(0x6d, 2, 3),
244 [PLDO2_DVS_CTR_SEL] = REG_FIELD(0x6c, 6, 7),
245 [PLDO1_DVS_CTR_SEL] = REG_FIELD(0x6c, 2, 3),
246 /* DVS_CTRL_SEL5 */
247 [PLDO6_DVS_CTR_SEL] = REG_FIELD(0x6e, 6, 7),
248 [PLDO5_DVS_CTR_SEL] = REG_FIELD(0x6e, 2, 3),
249 /* DVS_START_CTRL */
250 [DVS_START3] = REG_FIELD(0x70, 2, 2),
251 [DVS_START2] = REG_FIELD(0x70, 1, 1),
252 [DVS_START1] = REG_FIELD(0x70, 0, 0),
253 /* SLEEP_GPIO */
254 [SLP3_DATA] = REG_FIELD(0x71, 6, 6),
255 [SLP2_DATA] = REG_FIELD(0x71, 5, 5),
256 [SLP1_DATA] = REG_FIELD(0x71, 4, 4),
257 [SLP3_DR] = REG_FIELD(0x71, 2, 2),
258 [SLP2_DR] = REG_FIELD(0x71, 1, 1),
259 [SLP1_DR] = REG_FIELD(0x71, 0, 0),
260 /* SYS_CFG3 */
261 [RST_FUN] = REG_FIELD(0x72, 6, 7),
262 [DEV_RST] = REG_FIELD(0x72, 5, 5),
263 [DEV_SLP] = REG_FIELD(0x72, 4, 4),
264 [SLAVE_RESTART_FUN] = REG_FIELD(0x72, 1, 1),
265 [DEV_OFF] = REG_FIELD(0x72, 0, 0),
266 [WDT_CLR] = REG_FIELD(0x73, 4, 4),
267 [WDT_EN] = REG_FIELD(0x73, 3, 3),
268 [WDT_SET] = REG_FIELD(0x73, 0, 3),
269 [ON_SOURCE] = REG_FIELD(0x74, 0, 7),
270 [OFF_SOURCE] = REG_FIELD(0x75, 0, 7),
271 /* PWRON_KEY */
272 [PWRON_ON_TIME] = REG_FIELD(0x76, 7, 7),
273 [PWRON_LP_ACT] = REG_FIELD(0x76, 6, 6),
274 [PWRON_LP_OFF_TIME] = REG_FIELD(0x76, 4, 5),
275 [PWRON_LP_TM_SEL] = REG_FIELD(0x76, 2, 3),
276 [PWRON_DB_SEL] = REG_FIELD(0x76, 0, 1),
277
278 /* GPIO_INT_CONFIG */
279 [INT_FUNCTION] = REG_FIELD(0x7b, 2, 2),
280 [INT_POL] = REG_FIELD(0x7b, 1, 1),
281 [INT_FC_EN] = REG_FIELD(0x7b, 0, 0),
282 [BUCK9_RATE2] = REG_FIELD(0xEA, 0, 0),
283 [BUCK10_RATE2] = REG_FIELD(0xEA, 1, 1),
284 [LDO_RATE] = REG_FIELD(0xEA, 3, 5),
285 [BUCK1_RATE2] = REG_FIELD(0xEB, 0, 0),
286 [BUCK2_RATE2] = REG_FIELD(0xEB, 1, 1),
287 [BUCK3_RATE2] = REG_FIELD(0xEB, 2, 2),
288 [BUCK4_RATE2] = REG_FIELD(0xEB, 3, 3),
289 [BUCK5_RATE2] = REG_FIELD(0xEB, 4, 4),
290 [BUCK6_RATE2] = REG_FIELD(0xEB, 5, 5),
291 [BUCK7_RATE2] = REG_FIELD(0xEB, 6, 6),
292 [BUCK8_RATE2] = REG_FIELD(0xEB, 7, 7),
293 };
294
295 static struct resource rk806_pwrkey_resources[] = {
296 DEFINE_RES_IRQ(RK806_IRQ_PWRON_FALL),
297 DEFINE_RES_IRQ(RK806_IRQ_PWRON_RISE),
298 };
299
300 static const struct mfd_cell rk806_cells[] = {
301 { .name = "rk806-pinctrl", },
302 {
303 .name = "rk805-pwrkey",
304 .num_resources = ARRAY_SIZE(rk806_pwrkey_resources),
305 .resources = &rk806_pwrkey_resources[0],
306 },
307 { .name = "rk806-regulator", },
308
309 };
310
311 static const struct regmap_irq rk806_irqs[] = {
312 /* INT_STS0 IRQs */
313 REGMAP_IRQ_REG(RK806_IRQ_PWRON_FALL, 0, RK806_INT_STS_PWRON_FALL),
314 REGMAP_IRQ_REG(RK806_IRQ_PWRON_RISE, 0, RK806_INT_STS_PWRON_RISE),
315 REGMAP_IRQ_REG(RK806_IRQ_PWRON, 0, RK806_INT_STS_PWRON),
316 REGMAP_IRQ_REG(RK806_IRQ_PWRON_LP, 0, RK806_INT_STS_PWRON_LP),
317 REGMAP_IRQ_REG(RK806_IRQ_HOTDIE, 0, RK806_INT_STS_HOTDIE),
318 REGMAP_IRQ_REG(RK806_IRQ_VDC_RISE, 0, RK806_INT_STS_VDC_RISE),
319 REGMAP_IRQ_REG(RK806_IRQ_VDC_FALL, 0, RK806_INT_STS_VDC_FALL),
320 REGMAP_IRQ_REG(RK806_IRQ_VB_LO, 0, RK806_INT_STS_VB_LO),
321 /* INT_STS1 IRQs */
322 REGMAP_IRQ_REG(RK806_IRQ_REV0, 1, RK806_INT_STS_REV0),
323 REGMAP_IRQ_REG(RK806_IRQ_REV1, 1, RK806_INT_STS_REV1),
324 REGMAP_IRQ_REG(RK806_IRQ_REV2, 1, RK806_INT_STS_REV2),
325 REGMAP_IRQ_REG(RK806_IRQ_CRC_ERROR, 1, RK806_INT_STS_CRC_ERROR),
326 REGMAP_IRQ_REG(RK806_IRQ_SLP3_GPIO, 1, RK806_INT_STS_SLP3_GPIO),
327 REGMAP_IRQ_REG(RK806_IRQ_SLP2_GPIO, 1, RK806_INT_STS_SLP2_GPIO),
328 REGMAP_IRQ_REG(RK806_IRQ_SLP1_GPIO, 1, RK806_INT_STS_SLP1_GPIO),
329 REGMAP_IRQ_REG(RK806_IRQ_WDT, 1, RK806_INT_STS_WDT),
330 };
331
332 static struct regmap_irq_chip rk806_irq_chip = {
333 .name = "rk806",
334 .irqs = rk806_irqs,
335 .num_irqs = ARRAY_SIZE(rk806_irqs),
336 .num_regs = 2,
337 .irq_reg_stride = 2,
338 .mask_base = RK806_INT_MSK0,
339 .status_base = RK806_INT_STS0,
340 .ack_base = RK806_INT_STS0,
341 .init_ack_masked = true,
342 };
343
344 static const struct regmap_range rk806_yes_ranges[] = {
345 /* regmap_reg_range(RK806_INT_STS0, RK806_GPIO_INT_CONFIG), */
346 regmap_reg_range(0x70, 0x7a),
347 };
348
349 static const struct regmap_access_table rk806_volatile_table = {
350 .yes_ranges = rk806_yes_ranges,
351 .n_yes_ranges = ARRAY_SIZE(rk806_yes_ranges),
352 };
353
354 const struct regmap_config rk806_regmap_config_spi = {
355 .reg_bits = 8,
356 .val_bits = 8,
357 .cache_type = REGCACHE_RBTREE,
358 .volatile_table = &rk806_volatile_table,
359 };
360 EXPORT_SYMBOL_GPL(rk806_regmap_config_spi);
361
rk806_field_read(struct rk806 * rk806,enum rk806_fields field_id)362 int rk806_field_read(struct rk806 *rk806,
363 enum rk806_fields field_id)
364 {
365 int ret;
366 int val;
367
368 ret = regmap_field_read(rk806->rmap_fields[field_id], &val);
369 if (ret < 0)
370 return ret;
371
372 return val;
373 }
374 EXPORT_SYMBOL_GPL(rk806_field_read);
375
rk806_field_write(struct rk806 * rk806,enum rk806_fields field_id,unsigned int val)376 int rk806_field_write(struct rk806 *rk806,
377 enum rk806_fields field_id,
378 unsigned int val)
379 {
380 return regmap_field_write(rk806->rmap_fields[field_id], val);
381 }
382 EXPORT_SYMBOL_GPL(rk806_field_write);
383
rk806_irq_init(struct rk806 * rk806)384 static void rk806_irq_init(struct rk806 *rk806)
385 {
386 /* INT pin polarity active low */
387 rk806_field_write(rk806, INT_POL, RK806_INT_POL_LOW);
388 }
389
rk806_pinctrl_init(struct rk806 * rk806)390 static int rk806_pinctrl_init(struct rk806 *rk806)
391 {
392 struct device *dev = rk806->dev;
393
394 rk806->pins = devm_kzalloc(dev,
395 sizeof(struct rk806_pin_info),
396 GFP_KERNEL);
397 if (!rk806->pins)
398 return -ENOMEM;
399
400 rk806->pins->p = devm_pinctrl_get(dev);
401 if (IS_ERR(rk806->pins->p)) {
402 rk806->pins->p = NULL;
403 dev_err(dev, "rk806 no pinctrl handle\n");
404 return 0;
405 }
406
407 rk806->pins->default_st = pinctrl_lookup_state(rk806->pins->p,
408 PINCTRL_STATE_DEFAULT);
409
410 if (IS_ERR(rk806->pins->default_st))
411 dev_err(dev, "no default pinctrl state\n");
412
413 rk806->pins->power_off = pinctrl_lookup_state(rk806->pins->p,
414 "pmic-power-off");
415 if (IS_ERR(rk806->pins->power_off)) {
416 rk806->pins->power_off = NULL;
417 dev_err(dev, "no power-off pinctrl state\n");
418 }
419
420 rk806->pins->sleep = pinctrl_lookup_state(rk806->pins->p,
421 "pmic-sleep");
422 if (IS_ERR(rk806->pins->sleep)) {
423 rk806->pins->sleep = NULL;
424 dev_err(dev, "no sleep-setting state\n");
425 }
426
427 rk806->pins->reset = pinctrl_lookup_state(rk806->pins->p,
428 "pmic-reset");
429 if (IS_ERR(rk806->pins->reset)) {
430 rk806->pins->reset = NULL;
431 dev_err(dev, "no reset-setting pinctrl state\n");
432 }
433
434 rk806->pins->dvs = pinctrl_lookup_state(rk806->pins->p,
435 "pmic-dvs");
436 if (IS_ERR(rk806->pins->dvs)) {
437 rk806->pins->dvs = NULL;
438 dev_err(dev, "no dvs-setting pinctrl state\n");
439 }
440
441 return 0;
442 }
443
rk806_vb_low_irq(int irq,void * rk806)444 static irqreturn_t rk806_vb_low_irq(int irq, void *rk806)
445 {
446 return IRQ_HANDLED;
447 }
448
rk806_low_power_irqs(struct rk806 * rk806)449 static int rk806_low_power_irqs(struct rk806 *rk806)
450 {
451 struct rk806_platform_data *pdata;
452 int ret, vb_lo_irq;
453
454 pdata = rk806->pdata;
455
456 if (!pdata->low_voltage_threshold)
457 return 0;
458
459 rk806_field_write(rk806, VB_LO_ACT, VB_LO_ACT_INT);
460
461 rk806_field_write(rk806, VB_LO_SEL,
462 (pdata->low_voltage_threshold - 2800) / 100);
463
464 vb_lo_irq = regmap_irq_get_virq(rk806->irq_data, RK806_IRQ_VB_LO);
465 if (vb_lo_irq < 0) {
466 dev_err(rk806->dev, "vb_lo_irq request failed!\n");
467 return vb_lo_irq;
468 }
469
470 ret = devm_request_threaded_irq(rk806->dev, vb_lo_irq,
471 NULL,
472 rk806_vb_low_irq,
473 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
474 "rk806_vb_low", rk806);
475 if (ret) {
476 dev_err(rk806->dev, "vb_lo_irq request failed!\n");
477 return ret;
478 }
479
480 rk806->vb_lo_irq = vb_lo_irq;
481 disable_irq(rk806->vb_lo_irq);
482 enable_irq_wake(vb_lo_irq);
483
484 return 0;
485 }
486
rk806_parse_dt(struct rk806 * rk806)487 static int rk806_parse_dt(struct rk806 *rk806)
488 {
489 struct rk806_platform_data *pdata;
490 struct device *dev = rk806->dev;
491 int rst_fun;
492 int ret;
493
494 pdata = rk806->pdata;
495
496 pdata->shutdown_voltage_threshold = 2700;
497 pdata->shutdown_temperture_threshold = 160;
498 pdata->hotdie_temperture_threshold = 115;
499 pdata->force_shutdown_enable = 1;
500
501 ret = device_property_read_u32(dev,
502 "low_voltage_threshold",
503 &pdata->low_voltage_threshold);
504 if (ret < 0) {
505 pdata->low_voltage_threshold = 0;
506 dev_info(dev, "low_voltage_threshold missing!\n");
507 } else {
508 if ((pdata->low_voltage_threshold > 3500) ||
509 (pdata->low_voltage_threshold < 2800)) {
510 dev_err(dev, "low_voltage_threshold out [2800 3500]!\n");
511 pdata->low_voltage_threshold = 2800;
512 }
513 }
514 ret = device_property_read_u32(dev,
515 "shutdown_voltage_threshold",
516 &pdata->shutdown_voltage_threshold);
517 if (ret < 0) {
518 pdata->force_shutdown_enable = 0;
519 dev_info(dev, "shutdown_voltage_threshold missing!\n");
520 }
521
522 if ((pdata->shutdown_voltage_threshold > 3400) ||
523 (pdata->shutdown_voltage_threshold < 2700)) {
524 dev_err(dev, "shutdown_voltage_threshold out [2700 3400]!\n");
525 pdata->shutdown_voltage_threshold = 2700;
526 }
527
528 ret = device_property_read_u32(dev,
529 "shutdown_temperture_threshold",
530 &pdata->shutdown_temperture_threshold);
531 if (ret < 0)
532 dev_info(dev, "shutdown_temperture_threshold missing!\n");
533
534 ret = device_property_read_u32(dev,
535 "hotdie_temperture_threshold",
536 &pdata->hotdie_temperture_threshold);
537 if (ret < 0)
538 dev_info(dev, "hotdie_temperture_threshold missing!\n");
539
540 ret = device_property_read_u32(dev, "pmic-reset-func", &rst_fun);
541 if (ret < 0) {
542 dev_info(dev, "pmic-reset-func missing!\n");
543 rk806_field_write(rk806, RST_FUN, 0x00);
544 } else
545 rk806_field_write(rk806, RST_FUN, rst_fun);
546
547 return 0;
548 }
549
rk806_init(struct rk806 * rk806)550 static int rk806_init(struct rk806 *rk806)
551 {
552 struct rk806_platform_data *pdata;
553 int vb_uv_sel;
554
555 pdata = rk806->pdata;
556
557 if (pdata->force_shutdown_enable) {
558 if (pdata->shutdown_voltage_threshold <= 2700)
559 vb_uv_sel = VB_UV_SEL_2700;
560 else
561 vb_uv_sel = (pdata->shutdown_voltage_threshold - 2700) / 100;
562
563 rk806_field_write(rk806, VB_UV_SEL, vb_uv_sel);
564 }
565
566 if (pdata->hotdie_temperture_threshold >= 160)
567 rk806_field_write(rk806, TSD_TEMP, TSD_TEMP_160);
568
569 /* When the slave chip goes through a shutdown process, it will automatically trigger a restart */
570 rk806_field_write(rk806, SLAVE_RESTART_FUN, 0x01);
571 /* Digital output 2MHz clock force enable */
572 rk806_field_write(rk806, ENB2_2M, 0x01);
573
574 rk806_low_power_irqs(rk806);
575
576 return 0;
577 }
578
rk806_device_init(struct rk806 * rk806)579 int rk806_device_init(struct rk806 *rk806)
580 {
581 struct rk806_platform_data *pdata;
582 int name_h, name_l, chip_ver, otp_ver;
583 int on_source, off_source;
584 int ret;
585 int i;
586
587 pdata = devm_kzalloc(rk806->dev, sizeof(*pdata), GFP_KERNEL);
588 if (!pdata)
589 return -ENOMEM;
590
591 rk806->pdata = pdata;
592
593 for (i = 0; i < ARRAY_SIZE(rk806_reg_fields); i++) {
594 const struct reg_field *reg_fields = rk806_reg_fields;
595
596 rk806->rmap_fields[i] =
597 devm_regmap_field_alloc(rk806->dev,
598 rk806->regmap,
599 reg_fields[i]);
600 if (IS_ERR(rk806->rmap_fields[i])) {
601 dev_err(rk806->dev, "cannot allocate regmap field\n");
602 return PTR_ERR(rk806->rmap_fields[i]);
603 }
604 }
605
606 name_h = rk806_field_read(rk806, CHIP_NAME_H);
607 name_l = rk806_field_read(rk806, CHIP_NAME_L);
608 chip_ver = rk806_field_read(rk806, CHIP_VER);
609 otp_ver = rk806_field_read(rk806, OTP_VER);
610 dev_info(rk806->dev, "chip id: RK%x%x,ver:0x%x, 0x%x\n",
611 name_h, name_l, chip_ver, otp_ver);
612 if (chip_ver == VERSION_AB)
613 rk806_field_write(rk806, ABNORDET_EN, 0x01);
614
615 on_source = rk806_field_read(rk806, ON_SOURCE);
616 off_source = rk806_field_read(rk806, OFF_SOURCE);
617 dev_info(rk806->dev, "ON: 0x%x OFF:0x%x\n", on_source, off_source);
618
619 rk806_parse_dt(rk806);
620
621 rk806_irq_init(rk806);
622 ret = devm_regmap_add_irq_chip(rk806->dev,
623 rk806->regmap,
624 rk806->irq,
625 IRQF_ONESHOT | IRQF_SHARED,
626 0,
627 &rk806_irq_chip,
628 &rk806->irq_data);
629 if (ret) {
630 dev_err(rk806->dev, "Failed to add IRQ chip: err = %d\n", ret);
631 return ret;
632 }
633
634 ret = devm_mfd_add_devices(rk806->dev,
635 PLATFORM_DEVID_AUTO,
636 rk806_cells,
637 ARRAY_SIZE(rk806_cells),
638 NULL,
639 0,
640 regmap_irq_get_domain(rk806->irq_data));
641 if (ret < 0) {
642 dev_err(rk806->dev, "mfd_add_devices failed: %d\n", ret);
643 return ret;
644 }
645
646 rk806_pinctrl_init(rk806);
647 rk806_init(rk806);
648
649 return 0;
650 }
651 EXPORT_SYMBOL_GPL(rk806_device_init);
652
rk806_device_exit(struct rk806 * rk806)653 int rk806_device_exit(struct rk806 *rk806)
654 {
655 return 0;
656 }
657 EXPORT_SYMBOL_GPL(rk806_device_exit);
658
659 MODULE_AUTHOR("Xu Shengfei <xsf@rock-chips.com>");
660 MODULE_DESCRIPTION("rk806 MFD Driver");
661 MODULE_LICENSE("GPL v2");
662