1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2020 Rockchip Electronics Co. Ltd. 4 * 5 * Author: Algea Cao <algea.cao@rock-chips.com> 6 */ 7 8 #ifndef _rk630_H 9 #define _rk630_H 10 11 #include <linux/clk.h> 12 #include <linux/delay.h> 13 #include <linux/regmap.h> 14 #include <linux/mfd/core.h> 15 16 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) 17 #define HIWORD_MASK(h, l) ((GENMASK((h), (l)) << 16) | GENMASK((h), (l))) 18 #define HIWORD_UPDATE(v, h, l) ((((v) << (l)) & GENMASK((h), (l))) | (GENMASK((h), (l)) << 16)) 19 20 #define GRF_REG(x) ((x) + 0x20000) 21 #define PLUMAGE_GRF_GPIO0A_IOMUX GRF_REG(0x0000) 22 #define GPIO0A0_SEL_MASK HIWORD_MASK(1, 0) 23 #define GPIO0A0_SEL(x) HIWORD_UPDATE(x, 1, 0) 24 #define GPIO0A1_SEL_MASK HIWORD_MASK(3, 2) 25 #define GPIO0A1_SEL(x) HIWORD_UPDATE(x, 3, 2) 26 #define GPIO0A2_SEL_MASK HIWORD_MASK(5, 4) 27 #define GPIO0A2_SEL(x) HIWORD_UPDATE(x, 5, 4) 28 #define GPIO0A3_SEL_MASK HIWORD_MASK(7, 6) 29 #define GPIO0A3_SEL(x) HIWORD_UPDATE(x, 7, 6) 30 #define GPIO0A4_SEL_MASK HIWORD_MASK(9, 8) 31 #define GPIO0A4_SEL(x) HIWORD_UPDATE(x, 9, 8) 32 #define GPIO0A5_SEL_MASK HIWORD_MASK(11, 10) 33 #define GPIO0A5_SEL(x) HIWORD_UPDATE(x, 11, 10) 34 #define GPIO0A6_SEL_MASK HIWORD_MASK(13, 12) 35 #define GPIO0A6_SEL(x) HIWORD_UPDATE(x, 13, 12) 36 #define GPIO0A7_SEL_MASK HIWORD_MASK(15, 14) 37 #define GPIO0A7_SEL(x) HIWORD_UPDATE(x, 15, 14) 38 #define PLUMAGE_GRF_GPIO0B_IOMUX GRF_REG(0x0008) 39 #define GPIO0B0_SEL_MASK HIWORD_MASK(1, 0) 40 #define GPIO0B0_SEL(x) HIWORD_UPDATE(x, 1, 0) 41 #define PLUMAGE_GRF_GPIO0C_IOMUX GRF_REG(0x0010) 42 #define PLUMAGE_GRF_GPIO0D_IOMUX GRF_REG(0x0018) 43 #define PLUMAGE_GRF_GPIO1A_IOMUX GRF_REG(0x0020) 44 #define PLUMAGE_GRF_GPIO1B_IOMUX GRF_REG(0x0028) 45 #define PLUMAGE_GRF_GPIO0A_P GRF_REG(0x0080) 46 #define PLUMAGE_GRF_GPIO0B_P GRF_REG(0x0084) 47 #define PLUMAGE_GRF_GPIO0C_P GRF_REG(0x0088) 48 #define PLUMAGE_GRF_GPIO0D_P GRF_REG(0x008C) 49 #define PLUMAGE_GRF_GPIO1A_P GRF_REG(0x0090) 50 #define PLUMAGE_GRF_GPIO1B_P GRF_REG(0x0094) 51 #define PLUMAGE_GRF_GPIO1B_SR GRF_REG(0x00D4) 52 #define PLUMAGE_GRF_GPIO1B_E GRF_REG(0x0154) 53 #define PLUMAGE_GRF_SOC_CON0 GRF_REG(0x0400) 54 #define SW_TVE_DCLK_POL_MASK HIWORD_MASK(4, 4) 55 #define SW_TVE_DCLK_POL(x) HIWORD_UPDATE(x, 4, 4) 56 #define SW_TVE_DCLK_EN_MASK HIWORD_MASK(3, 3) 57 #define SW_TVE_DCLK_EN(x) HIWORD_UPDATE(x, 3, 3) 58 #define SW_DCLK_UPSAMPLE_EN_MASK HIWORD_MASK(2, 2) 59 #define SW_DCLK_UPSAMPLE_EN(x) HIWORD_UPDATE(x, 2, 2) 60 #define SW_TVE_MODE_MASK HIWORD_MASK(1, 1) 61 #define SW_TVE_MODE(x) HIWORD_UPDATE(x, 1, 1) 62 #define SW_TVE_EN_MASK HIWORD_MASK(0, 0) 63 #define SW_TVE_EN(x) HIWORD_UPDATE(x, 0, 0) 64 #define PLUMAGE_GRF_SOC_CON1 GRF_REG(0x0404) 65 #define PLUMAGE_GRF_SOC_CON2 GRF_REG(0x0408) 66 #define PLUMAGE_GRF_SOC_CON3 GRF_REG(0x040C) 67 #define VDAC_ENVBG_MASK HIWORD_MASK(12, 12) 68 #define VDAC_ENVBG(x) HIWORD_UPDATE(x, 12, 12) 69 #define VDAC_ENSC0_MASK HIWORD_MASK(11, 11) 70 #define VDAC_ENSC0(x) HIWORD_UPDATE(x, 11, 11) 71 #define VDAC_ENEXTREF_MASK HIWORD_MASK(10, 10) 72 #define VDAC_ENEXTREF(x) HIWORD_UPDATE(x, 10, 10) 73 #define VDAC_ENDAC0_MASK HIWORD_MASK(9, 9) 74 #define VDAC_ENDAC0(x) HIWORD_UPDATE(x, 9, 9) 75 #define VDAC_ENCTR2_MASK HIWORD_MASK(8, 8) 76 #define VDAC_ENCTR2(x) HIWORD_UPDATE(x, 8, 8) 77 #define VDAC_ENCTR1_MASK HIWORD_MASK(7, 7) 78 #define VDAC_ENCTR1(x) HIWORD_UPDATE(x, 7, 7) 79 #define VDAC_ENCTR0_MASK HIWORD_MASK(6, 6) 80 #define VDAC_ENCTR0(x) HIWORD_UPDATE(x, 6, 6) 81 #define VDAC_GAIN_MASK GENMASK(x, 5, 0) 82 #define VDAC_GAIN(x) HIWORD_UPDATE(x, 5, 0) 83 #define PLUMAGE_GRF_SOC_CON4 GRF_REG(0x0410) 84 #define PLUMAGE_GRF_SOC_STATUS GRF_REG(0x0480) 85 #define PLUMAGE_GRF_GPIO0_REN0 GRF_REG(0x0500) 86 #define PLUMAGE_GRF_GPIO0_REN1 GRF_REG(0x0504) 87 #define PLUMAGE_GRF_GPIO1_REN0 GRF_REG(0x0508) 88 #define GRF_MAX_REGISTER PLUMAGE_GRF_GPIO1_REN0 89 90 #define CRU_REG(x) ((x) + 0x140000) 91 #define CRU_SPLL_CON0 CRU_REG(0x0000) 92 #define POSTDIV1_MASK HIWORD_MASK(14, 12) 93 #define POSTDIV1(x) HIWORD_UPDATE(x, 14, 12) 94 #define FBDIV_MASK HIWORD_MASK(14, 12) 95 #define FBDIV(x) HIWORD_UPDATE(x, 14, 12) 96 #define CRU_SPLL_CON1 CRU_REG(0x0004) 97 #define PLLPD0_MASK HIWORD_MASK(13, 13) 98 #define PLLPD0(x) HIWORD_UPDATE(x, 13, 13) 99 #define PLL_LOCK BIT(10) 100 #define POSTDIV2_MASK HIWORD_MASK(8, 6) 101 #define POSTDIV2(x) HIWORD_UPDATE(x, 8, 6) 102 #define REFDIV_MASK HIWORD_MASK(5, 0) 103 #define REFDIV(x) HIWORD_UPDATE(x, 5, 0) 104 #define CRU_SPLL_CON2 CRU_REG(0x0008) 105 #define CRU_MODE_CON CRU_REG(0x0020) 106 #define CLK_SPLL_MODE_MASK HIWORD_MASK(2, 0) 107 #define CLK_SPLL_MODE(x) HIWORD_UPDATE(x, 2, 0) 108 #define CRU_CLKSEL_CON0 CRU_REG(0x0030) 109 #define CRU_CLKSEL_CON1 CRU_REG(0x0034) 110 #define DCLK_CVBS_4X_DIV_CON_MASK HIWORD_MASK(12, 8) 111 #define DCLK_CVBS_4X_DIV_CON(x) HIWORD_UPDATE(x, 12, 8) 112 #define CRU_CLKSEL_CON2 CRU_REG(0x0038) 113 #define CRU_CLKSEL_CON3 CRU_REG(0x003c) 114 #define CRU_GATE_CON0 CRU_REG(0x0040) 115 #define CRU_SOFTRST_CON0 CRU_REG(0x0050) 116 #define DRESETN_CVBS_1X_MASK HIWORD_MASK(10, 10) 117 #define DRESETN_CVBS_1X(x) HIWORD_UPDATE(x, 10, 10) 118 #define DRESETN_CVBS_4X_MASK HIWORD_MASK(9, 9) 119 #define DRESETN_CVBS_4X(x) HIWORD_UPDATE(x, 9, 9) 120 #define PRESETN_CVBS_MASK HIWORD_MASK(8, 8) 121 #define PRESETN_CVBS(x) HIWORD_UPDATE(x, 8, 8) 122 #define PRESETN_GRF_MASK HIWORD_MASK(3, 3) 123 #define PRESETN_GRF(x) HIWORD_UPDATE(x, 3, 3) 124 #define CRU_MAX_REGISTER CRU_SOFTRST_CON0 125 126 #define TVE_REG(x) ((x) + 0x10000) 127 #define BT656_DECODER_CTRL TVE_REG(0x3D00) 128 #define BT656_DECODER_CROP TVE_REG(0x3D04) 129 #define BT656_DECODER_SIZE TVE_REG(0x3D08) 130 #define BT656_DECODER_HTOTAL_HS_END TVE_REG(0x3D0C) 131 #define BT656_DECODER_VACT_ST_HACT_ST TVE_REG(0x3D10) 132 #define BT656_DECODER_VTOTAL_VS_END TVE_REG(0x3D14) 133 #define BT656_DECODER_VS_ST_END_F1 TVE_REG(0x3D18) 134 #define BT656_DECODER_DBG_REG TVE_REG(0x3D1C) 135 #define TVE_MODE_CTRL TVE_REG(0x3E00) 136 #define TVE_HOR_TIMING1 TVE_REG(0x3E04) 137 #define TVE_HOR_TIMING2 TVE_REG(0x3E08) 138 #define TVE_HOR_TIMING3 TVE_REG(0x3E0C) 139 #define TVE_SUB_CAR_FRQ TVE_REG(0x3E10) 140 #define TVE_LUMA_FILTER1 TVE_REG(0x3E14) 141 #define TVE_LUMA_FILTER2 TVE_REG(0x3E18) 142 #define TVE_LUMA_FILTER3 TVE_REG(0x3E1C) 143 #define TVE_LUMA_FILTER4 TVE_REG(0x3E20) 144 #define TVE_LUMA_FILTER5 TVE_REG(0x3E24) 145 #define TVE_LUMA_FILTER6 TVE_REG(0x3E28) 146 #define TVE_LUMA_FILTER7 TVE_REG(0x3E2C) 147 #define TVE_LUMA_FILTER8 TVE_REG(0x3E30) 148 #define TVE_IMAGE_POSITION TVE_REG(0x3E34) 149 #define TVE_ROUTING TVE_REG(0x3E38) 150 #define TVE_SYNC_ADJUST TVE_REG(0x3E50) 151 #define TVE_STATUS TVE_REG(0x3E54) 152 #define TVE_CTRL TVE_REG(0x3E68) 153 #define TVE_INTR_STATUS TVE_REG(0x3E6C) 154 #define TVE_INTR_EN TVE_REG(0x3E70) 155 #define TVE_INTR_CLR TVE_REG(0x3E74) 156 #define TVE_COLOR_BUSRT_SAT TVE_REG(0x3E78) 157 #define TVE_CHROMA_BANDWIDTH TVE_REG(0x3E8C) 158 #define TVE_BRIGHTNESS_CONTRAST TVE_REG(0x3E90) 159 #define TVE_ID TVE_REG(0x3E98) 160 #define TVE_REVISION TVE_REG(0x3E9C) 161 #define TVE_CLAMP TVE_REG(0x3EA0) 162 #define TVE_MAX_REGISTER TVE_CLAMP 163 164 struct rk630 { 165 struct device *dev; 166 struct i2c_client *client; 167 struct regmap *grf; 168 struct regmap *cru; 169 struct regmap *tve; 170 struct gpio_desc *reset_gpio; 171 }; 172 173 extern const struct regmap_config rk630_grf_regmap_config; 174 extern const struct regmap_config rk630_cru_regmap_config; 175 extern const struct regmap_config rk630_tve_regmap_config; 176 177 int rk630_core_probe(struct rk630 *rk630); 178 int rk630_core_remove(struct rk630 *rk630); 179 180 #endif 181