1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6 #ifndef __LINUX_REGULATOR_RK806_H 7 #define __LINUX_REGULATOR_RK806_H 8 9 #include <linux/regmap.h> 10 #include <linux/regulator/driver.h> 11 #include <linux/regulator/machine.h> 12 13 #define RK806_POWER_EN0 0x0 14 #define RK806_POWER_EN1 0x1 15 #define RK806_POWER_EN2 0x2 16 #define RK806_POWER_EN3 0x3 17 #define RK806_POWER_EN4 0x4 18 #define RK806_POWER_EN5 0x5 19 #define RK806_POWER_SLP_EN0 0x6 20 #define RK806_POWER_SLP_EN1 0x7 21 #define RK806_POWER_SLP_EN2 0x8 22 #define RK806_POWER_DISCHRG_EN0 0x9 23 #define RK806_POWER_DISCHRG_EN1 0xA 24 #define RK806_POWER_DISCHRG_EN2 0xB 25 #define RK806_BUCK_FB_CONFIG 0xC 26 #define RK806_SLP_LP_CONFIG 0xD 27 #define RK806_POWER_FPWM_EN0 0xE 28 #define RK806_POWER_FPWM_EN1 0xF 29 #define RK806_BUCK1_CONFIG 0x10 30 #define RK806_BUCK2_CONFIG 0x11 31 #define RK806_BUCK3_CONFIG 0x12 32 #define RK806_BUCK4_CONFIG 0x13 33 #define RK806_BUCK5_CONFIG 0x14 34 #define RK806_BUCK6_CONFIG 0x15 35 #define RK806_BUCK7_CONFIG 0x16 36 #define RK806_BUCK8_CONFIG 0x17 37 #define RK806_BUCK9_CONFIG 0x18 38 #define RK806_BUCK10_CONFIG 0x19 39 #define RK806_BUCK1_ON_VSEL 0x1A 40 #define RK806_BUCK2_ON_VSEL 0x1B 41 #define RK806_BUCK3_ON_VSEL 0x1C 42 #define RK806_BUCK4_ON_VSEL 0x1D 43 #define RK806_BUCK5_ON_VSEL 0x1E 44 #define RK806_BUCK6_ON_VSEL 0x1F 45 #define RK806_BUCK7_ON_VSEL 0x20 46 #define RK806_BUCK8_ON_VSEL 0x21 47 #define RK806_BUCK9_ON_VSEL 0x22 48 #define RK806_BUCK10_ON_VSEL 0x23 49 #define RK806_BUCK1_SLP_VSEL 0x24 50 #define RK806_BUCK2_SLP_VSEL 0x25 51 #define RK806_BUCK3_SLP_VSEL 0x26 52 #define RK806_BUCK4_SLP_VSEL 0x27 53 #define RK806_BUCK5_SLP_VSEL 0x28 54 #define RK806_BUCK6_SLP_VSEL 0x29 55 #define RK806_BUCK7_SLP_VSEL 0x2A 56 #define RK806_BUCK8_SLP_VSEL 0x2B 57 #define RK806_BUCK9_SLP_VSEL 0x2D 58 #define RK806_BUCK10_SLP_VSEL 0x2E 59 #define RK806_BUCK_DEBUG1 0x30 60 #define RK806_BUCK_DEBUG2 0x31 61 #define RK806_BUCK_DEBUG3 0x32 62 #define RK806_BUCK_DEBUG4 0x33 63 #define RK806_BUCK_DEBUG5 0x34 64 #define RK806_BUCK_DEBUG6 0x35 65 #define RK806_BUCK_DEBUG7 0x36 66 #define RK806_BUCK_DEBUG8 0x37 67 #define RK806_BUCK_DEBUG9 0x38 68 #define RK806_BUCK_DEBUG10 0x39 69 #define RK806_BUCK_DEBUG11 0x3A 70 #define RK806_BUCK_DEBUG12 0x3B 71 #define RK806_BUCK_DEBUG13 0x3C 72 #define RK806_BUCK_DEBUG14 0x3D 73 #define RK806_BUCK_DEBUG15 0x3E 74 #define RK806_BUCK_DEBUG16 0x3F 75 #define RK806_BUCK_DEBUG17 0x40 76 #define RK806_BUCK_DEBUG18 0x41 77 #define RK806_NLDO_IMAX 0x42 78 #define RK806_NLDO1_ON_VSEL 0x43 79 #define RK806_NLDO2_ON_VSEL 0x44 80 #define RK806_NLDO3_ON_VSEL 0x45 81 #define RK806_NLDO4_ON_VSEL 0x46 82 #define RK806_NLDO5_ON_VSEL 0x47 83 #define RK806_NLDO1_SLP_VSEL 0x48 84 #define RK806_NLDO2_SLP_VSEL 0x49 85 #define RK806_NLDO3_SLP_VSEL 0x4A 86 #define RK806_NLDO4_SLP_VSEL 0x4B 87 #define RK806_NLDO5_SLP_VSEL 0x4C 88 #define RK806_PLDO_IMAX 0x4D 89 #define RK806_PLDO1_ON_VSEL 0x4E 90 #define RK806_PLDO2_ON_VSEL 0x4F 91 #define RK806_PLDO3_ON_VSEL 0x50 92 #define RK806_PLDO4_ON_VSEL 0x51 93 #define RK806_PLDO5_ON_VSEL 0x52 94 #define RK806_PLDO6_ON_VSEL 0x53 95 #define RK806_PLDO1_SLP_VSEL 0x54 96 #define RK806_PLDO2_SLP_VSEL 0x55 97 #define RK806_PLDO3_SLP_VSEL 0x56 98 #define RK806_PLDO4_SLP_VSEL 0x57 99 #define RK806_PLDO5_SLP_VSEL 0x58 100 #define RK806_PLDO6_SLP_VSEL 0x59 101 #define RK806_CHIP_NAME 0x5A 102 #define RK806_CHIP_VER 0x5B 103 #define RK806_OTP_VER 0x5C 104 #define RK806_SYS_STS 0x5D 105 #define RK806_SYS_CFG0 0x5E 106 #define RK806_SYS_CFG1 0x5F 107 #define RK806_SYS_OPTION 0x61 108 #define RK806_SLEEP_CONFIG0 0x62 109 #define RK806_SLEEP_CONFIG1 0x63 110 #define RK806_SLEEP_CTR_SEL0 0x64 111 #define RK806_SLEEP_CTR_SEL1 0x65 112 #define RK806_SLEEP_CTR_SEL2 0x66 113 #define RK806_SLEEP_CTR_SEL3 0x67 114 #define RK806_SLEEP_CTR_SEL4 0x68 115 #define RK806_SLEEP_CTR_SEL5 0x69 116 #define RK806_DVS_CTRL_SEL0 0x6A 117 #define RK806_DVS_CTRL_SEL1 0x6B 118 #define RK806_DVS_CTRL_SEL2 0x6C 119 #define RK806_DVS_CTRL_SEL3 0x6D 120 #define RK806_DVS_CTRL_SEL4 0x6E 121 #define RK806_DVS_CTRL_SEL5 0x6F 122 #define RK806_DVS_START_CTRL 0x70 123 #define RK806_SLEEP_GPIO 0x71 124 #define RK806_SYS_CFG3 0x72 125 #define RK806_ON_SOURCE 0x74 126 #define RK806_OFF_SOURCE 0x75 127 #define RK806_PWRON_KEY 0x76 128 #define RK806_INT_STS0 0x77 129 #define RK806_INT_MSK0 0x78 130 #define RK806_INT_STS1 0x79 131 #define RK806_INT_MSK1 0x7A 132 #define RK806_GPIO_INT_CONFIG 0x7B 133 #define RK806_DATA_REG0 0x7C 134 #define RK806_DATA_REG1 0x7D 135 #define RK806_DATA_REG2 0x7E 136 #define RK806_DATA_REG3 0x7F 137 #define RK806_DATA_REG4 0x80 138 #define RK806_DATA_REG5 0x81 139 #define RK806_DATA_REG6 0x82 140 #define RK806_DATA_REG7 0x83 141 #define RK806_DATA_REG8 0x84 142 #define RK806_DATA_REG9 0x85 143 #define RK806_DATA_REG10 0x86 144 #define RK806_DATA_REG11 0x87 145 #define RK806_DATA_REG12 0x88 146 #define RK806_DATA_REG13 0x89 147 #define RK806_DATA_REG14 0x8A 148 #define RK806_DATA_REG15 0x8B 149 #define RK806_TM_REG 0x8C 150 #define RK806_OTP_EN_REG 0x8D 151 #define RK806_FUNC_OTP_EN_REG 0x8E 152 #define RK806_TEST_REG1 0x8F 153 #define RK806_TEST_REG2 0x90 154 #define RK806_TEST_REG3 0x91 155 #define RK806_TEST_REG4 0x92 156 #define RK806_TEST_REG5 0x93 157 #define RK806_BUCK_VSEL_OTP_REG0 0x94 158 #define RK806_BUCK_VSEL_OTP_REG1 0x95 159 #define RK806_BUCK_VSEL_OTP_REG2 0x96 160 #define RK806_BUCK_VSEL_OTP_REG3 0x97 161 #define RK806_BUCK_VSEL_OTP_REG4 0x98 162 #define RK806_BUCK_VSEL_OTP_REG5 0x99 163 #define RK806_BUCK_VSEL_OTP_REG6 0x9A 164 #define RK806_BUCK_VSEL_OTP_REG7 0x9B 165 #define RK806_BUCK_VSEL_OTP_REG8 0x9C 166 #define RK806_BUCK_VSEL_OTP_REG9 0x9D 167 #define RK806_NLDO1_VSEL_OTP_REG0 0x9E 168 #define RK806_NLDO1_VSEL_OTP_REG1 0x9F 169 #define RK806_NLDO1_VSEL_OTP_REG2 0xA0 170 #define RK806_NLDO1_VSEL_OTP_REG3 0xA1 171 #define RK806_NLDO1_VSEL_OTP_REG4 0xA2 172 #define RK806_PLDO_VSEL_OTP_REG0 0xA3 173 #define RK806_PLDO_VSEL_OTP_REG1 0xA4 174 #define RK806_PLDO_VSEL_OTP_REG2 0xA5 175 #define RK806_PLDO_VSEL_OTP_REG3 0xA6 176 #define RK806_PLDO_VSEL_OTP_REG4 0xA7 177 #define RK806_PLDO_VSEL_OTP_REG5 0xA8 178 #define RK806_BUCK_EN_OTP_REG1 0xA9 179 #define RK806_NLDO_EN_OTP_REG1 0xAA 180 #define RK806_PLDO_EN_OTP_REG1 0xAB 181 #define RK806_BUCK_FB_RES_OTP_REG1 0xAC 182 #define RK806_OTP_RESEV_REG0 0xAD 183 #define RK806_OTP_RESEV_REG1 0xAE 184 #define RK806_OTP_RESEV_REG2 0xAF 185 #define RK806_OTP_RESEV_REG3 0xB0 186 #define RK806_OTP_RESEV_REG4 0xB1 187 #define RK806_BUCK_SEQ_REG0 0xB2 188 #define RK806_BUCK_SEQ_REG1 0xB3 189 #define RK806_BUCK_SEQ_REG2 0xB4 190 #define RK806_BUCK_SEQ_REG3 0xB5 191 #define RK806_BUCK_SEQ_REG4 0xB6 192 #define RK806_BUCK_SEQ_REG5 0xB7 193 #define RK806_BUCK_SEQ_REG6 0xB8 194 #define RK806_BUCK_SEQ_REG7 0xB9 195 #define RK806_BUCK_SEQ_REG8 0xBA 196 #define RK806_BUCK_SEQ_REG9 0xBB 197 #define RK806_BUCK_SEQ_REG10 0xBC 198 #define RK806_BUCK_SEQ_REG11 0xBD 199 #define RK806_BUCK_SEQ_REG12 0xBE 200 #define RK806_BUCK_SEQ_REG13 0xBF 201 #define RK806_BUCK_SEQ_REG14 0xC0 202 #define RK806_BUCK_SEQ_REG15 0xC1 203 #define RK806_BUCK_SEQ_REG16 0xC2 204 #define RK806_BUCK_SEQ_REG17 0xC3 205 #define RK806_HK_TRIM_REG1 0xC4 206 #define RK806_HK_TRIM_REG2 0xC5 207 #define RK806_BUCK_REF_TRIM_REG1 0xC6 208 #define RK806_BUCK_REF_TRIM_REG2 0xC7 209 #define RK806_BUCK_REF_TRIM_REG3 0xC8 210 #define RK806_BUCK_REF_TRIM_REG4 0xC9 211 #define RK806_BUCK_REF_TRIM_REG5 0xCA 212 #define RK806_BUCK_OSC_TRIM_REG1 0xCB 213 #define RK806_BUCK_OSC_TRIM_REG2 0xCC 214 #define RK806_BUCK_OSC_TRIM_REG3 0xCD 215 #define RK806_BUCK_OSC_TRIM_REG4 0xCE 216 #define RK806_BUCK_OSC_TRIM_REG5 0xCF 217 #define RK806_BUCK_TRIM_ZCDIOS_REG1 0xD0 218 #define RK806_BUCK_TRIM_ZCDIOS_REG2 0xD1 219 #define RK806_NLDO_TRIM_REG1 0xD2 220 #define RK806_NLDO_TRIM_REG2 0xD3 221 #define RK806_NLDO_TRIM_REG3 0xD4 222 #define RK806_PLDO_TRIM_REG1 0xD5 223 #define RK806_PLDO_TRIM_REG2 0xD6 224 #define RK806_PLDO_TRIM_REG3 0xD7 225 #define RK806_TRIM_ICOMP_REG1 0xD8 226 #define RK806_TRIM_ICOMP_REG2 0xD9 227 #define RK806_EFUSE_CONTROL_REGH 0xDA 228 #define RK806_FUSE_PROG_REG 0xDB 229 #define RK806_MAIN_FSM_STS_REG 0xDD 230 #define RK806_FSM_REG 0xDE 231 #define RK806_TOP_RESEV_OFFR 0xEC 232 #define RK806_TOP_RESEV_POR 0xED 233 #define RK806_BUCK_VRSN_REG1 0xEE 234 #define RK806_BUCK_VRSN_REG2 0xEF 235 #define RK806_NLDO_RLOAD_SEL_REG1 0xF0 236 #define RK806_PLDO_RLOAD_SEL_REG1 0xF1 237 #define RK806_PLDO_RLOAD_SEL_REG2 0xF2 238 #define RK806_BUCK_CMIN_MX_REG1 0xF3 239 #define RK806_BUCK_CMIN_MX_REG2 0xF4 240 #define RK806_BUCK_FREQ_SET_REG1 0xF5 241 #define RK806_BUCK_FREQ_SET_REG2 0xF6 242 #define RK806_BUCK_RS_MEABS_REG1 0xF7 243 #define RK806_BUCK_RS_MEABS_REG2 0xF8 244 #define RK806_BUCK_RS_ZDLEB_REG1 0xF9 245 #define RK806_BUCK_RS_ZDLEB_REG2 0xFA 246 #define RK806_BUCK_RSERVE_REG1 0xFB 247 #define RK806_BUCK_RSERVE_REG2 0xFC 248 #define RK806_BUCK_RSERVE_REG3 0xFD 249 #define RK806_BUCK_RSERVE_REG4 0xFE 250 #define RK806_BUCK_RSERVE_REG5 0xFF 251 252 /* INT_STS Register field definitions */ 253 #define RK806_INT_STS_PWRON_FALL BIT(0) 254 #define RK806_INT_STS_PWRON_RISE BIT(1) 255 #define RK806_INT_STS_PWRON BIT(2) 256 #define RK806_INT_STS_PWRON_LP BIT(3) 257 #define RK806_INT_STS_HOTDIE BIT(4) 258 #define RK806_INT_STS_VDC_RISE BIT(5) 259 #define RK806_INT_STS_VDC_FALL BIT(6) 260 #define RK806_INT_STS_VB_LO BIT(7) 261 #define RK806_INT_STS_REV0 BIT(0) 262 #define RK806_INT_STS_REV1 BIT(1) 263 #define RK806_INT_STS_REV2 BIT(2) 264 #define RK806_INT_STS_CRC_ERROR BIT(3) 265 #define RK806_INT_STS_SLP3_GPIO BIT(4) 266 #define RK806_INT_STS_SLP2_GPIO BIT(5) 267 #define RK806_INT_STS_SLP1_GPIO BIT(6) 268 #define RK806_INT_STS_WDT BIT(7) 269 270 /* spi command */ 271 #define RK806_CMD_READ 0 272 #define RK806_CMD_WRITE BIT(7) 273 #define RK806_CMD_CRC_EN BIT(6) 274 #define RK806_CMD_CRC_DIS 0 275 #define RK806_CMD_LEN_MSK 0x0f 276 #define RK806_REG_H 0x00 277 278 #define VERSION_AB 0x01 279 280 enum rk806_reg_id { 281 RK806_ID_DCDC1 = 0, 282 RK806_ID_DCDC2, 283 RK806_ID_DCDC3, 284 RK806_ID_DCDC4, 285 RK806_ID_DCDC5, 286 RK806_ID_DCDC6, 287 RK806_ID_DCDC7, 288 RK806_ID_DCDC8, 289 RK806_ID_DCDC9, 290 RK806_ID_DCDC10, 291 292 RK806_ID_NLDO1, 293 RK806_ID_NLDO2, 294 RK806_ID_NLDO3, 295 RK806_ID_NLDO4, 296 RK806_ID_NLDO5, 297 298 RK806_ID_PLDO1, 299 RK806_ID_PLDO2, 300 RK806_ID_PLDO3, 301 RK806_ID_PLDO4, 302 RK806_ID_PLDO5, 303 RK806_ID_PLDO6, 304 RK806_ID_END, 305 }; 306 307 /* Define the rk806 IRQ numbers */ 308 enum rk806_irqs { 309 /* INT_STS0 registers */ 310 RK806_IRQ_PWRON_FALL, 311 RK806_IRQ_PWRON_RISE, 312 RK806_IRQ_PWRON, 313 RK806_IRQ_PWRON_LP, 314 RK806_IRQ_HOTDIE, 315 RK806_IRQ_VDC_RISE, 316 RK806_IRQ_VDC_FALL, 317 RK806_IRQ_VB_LO, 318 319 /* INT_STS0 registers */ 320 RK806_IRQ_REV0, 321 RK806_IRQ_REV1, 322 RK806_IRQ_REV2, 323 RK806_IRQ_CRC_ERROR, 324 RK806_IRQ_SLP3_GPIO, 325 RK806_IRQ_SLP2_GPIO, 326 RK806_IRQ_SLP1_GPIO, 327 RK806_IRQ_WDT, 328 }; 329 330 /* VCC1 low voltage threshold */ 331 enum rk806_lv_sel { 332 VB_LO_SEL_2800, 333 VB_LO_SEL_2900, 334 VB_LO_SEL_3000, 335 VB_LO_SEL_3100, 336 VB_LO_SEL_3200, 337 VB_LO_SEL_3300, 338 VB_LO_SEL_3400, 339 VB_LO_SEL_3500, 340 }; 341 342 /* system shut down voltage select */ 343 enum rk806_uv_sel { 344 VB_UV_SEL_2700, 345 VB_UV_SEL_2800, 346 VB_UV_SEL_2900, 347 VB_UV_SEL_3000, 348 VB_UV_SEL_3100, 349 VB_UV_SEL_3200, 350 VB_UV_SEL_3300, 351 VB_UV_SEL_3400, 352 }; 353 354 /* pin function */ 355 enum rk806_pwrctrl_fun { 356 PWRCTRL_NULL_FUN, 357 PWRCTRL_SLP_FUN, 358 PWRCTRL_POWOFF_FUN, 359 PWRCTRL_RST_FUN, 360 PWRCTRL_DVS_FUN, 361 PWRCTRL_GPIO_FUN, 362 }; 363 364 /* pin pol */ 365 enum rk806_pin_level { 366 POL_LOW, 367 POL_HIGH, 368 }; 369 370 enum rk806_vsel_ctr_sel { 371 CTR_BY_NO_EFFECT, 372 CTR_BY_PWRCTRL1, 373 CTR_BY_PWRCTRL2, 374 CTR_BY_PWRCTRL3, 375 }; 376 377 enum rk806_dvs_ctr_sel { 378 CTR_SEL_NO_EFFECT, 379 CTR_SEL_DVS_START1, 380 CTR_SEL_DVS_START2, 381 CTR_SEL_DVS_START3, 382 }; 383 384 enum rk806_pin_dr_sel { 385 RK806_PIN_INPUT, 386 RK806_PIN_OUTPUT, 387 }; 388 389 enum rk806_int_pol { 390 RK806_INT_POL_LOW, 391 RK806_INT_POL_HIGH, 392 }; 393 394 enum rk806_int_fun { 395 RK806_INT_ONLY, 396 RK806_INT_ADN_WKUP, 397 }; 398 399 enum rk806_dvs_mode { 400 RK806_DVS_NOT_SUPPORT, 401 RK806_DVS_START1, 402 RK806_DVS_START2, 403 RK806_DVS_START3, 404 RK806_DVS_PWRCTRL1, 405 RK806_DVS_PWRCTRL2, 406 RK806_DVS_PWRCTRL3, 407 RK806_DVS_START_PWRCTR1, 408 RK806_DVS_START_PWRCTR2, 409 RK806_DVS_START_PWRCTR3, 410 RK806_DVS_END, 411 }; 412 413 enum rk806_fields { 414 CHIP_NAME_H, CHIP_NAME_L, CHIP_VER, OTP_VER, 415 POWER_EN0, POWER_EN1, POWER_EN2, POWER_EN3, POWER_EN4, POWER_EN5, 416 BUCK4_EN_MASK, BUCK3_EN_MASK, BUCK2_EN_MASK, BUCK1_EN_MASK, 417 BUCK4_EN, BUCK3_EN, BUCK2_EN, BUCK1_EN, 418 BUCK8_EN_MASK, BUCK7_EN_MASK, BUCK6_EN_MASK, BUCK5_EN_MASK, 419 BUCK8_EN, BUCK7_EN, BUCK6_EN, BUCK5_EN, 420 BUCK10_EN_MASK, BUCK9_EN_MASK, BUCK10_EN, BUCK9_EN, 421 NLDO4_EN_MASK, NLDO3_EN_MASK, NLDO2_EN_MASK, NLDO1_EN_MASK, 422 NLDO4_EN, NLDO3_EN, NLDO2_EN, NLDO1_EN, 423 PLDO4_EN_MASK, PLDO3_EN_MASK, PLDO2_EN_MASK, PLDO1_EN_MASK, 424 PLDO4_EN, PLDO3_EN, PLDO2_EN, PLDO1_EN, 425 NLDO5_EN_MASK, PLDO6_EN_MASK, PLDO5_EN_MASK, 426 NLDO5_EN, PLDO6_EN, PLDO5_EN, 427 BUCK8_SLP_EN, BUCK7_SLP_EN, BUCK6_SLP_EN, BUCK5_SLP_EN, BUCK4_SLP_EN, 428 BUCK3_SLP_EN, BUCK2_SLP_EN, BUCK1_SLP_EN, 429 BUCK10_SLP_EN, BUCK9_SLP_EN, NLDO5_SLP_EN, NLDO4_SLP_EN, NLDO3_SLP_EN, 430 NLDO2_SLP_EN, NLDO1_SLP_EN, 431 PLDO6_SLP_EN, PLDO5_SLP_EN, PLDO4_SLP_EN, PLDO3_SLP_EN, 432 PLDO2_SLP_EN, PLDO1_SLP_EN, 433 BUCK1_ON_VSEL, BUCK2_ON_VSEL, BUCK3_ON_VSEL, BUCK4_ON_VSEL, BUCK5_ON_VSEL, 434 BUCK6_ON_VSEL, BUCK7_ON_VSEL, BUCK8_ON_VSEL, BUCK9_ON_VSEL, BUCK10_ON_VSEL, 435 BUCK1_SLP_VSEL, BUCK2_SLP_VSEL, BUCK3_SLP_VSEL, BUCK4_SLP_VSEL, BUCK5_SLP_VSEL, 436 BUCK6_SLP_VSEL, BUCK7_SLP_VSEL, BUCK8_SLP_VSEL, BUCK9_SLP_VSEL, BUCK10_SLP_VSEL, 437 NLDO1_ON_VSEL, NLDO2_ON_VSEL, NLDO3_ON_VSEL, NLDO4_ON_VSEL, NLDO5_ON_VSEL, 438 NLDO1_SLP_VSEL, NLDO2_SLP_VSEL, NLDO3_SLP_VSEL, NLDO4_SLP_VSEL, NLDO5_SLP_VSEL, 439 PLDO1_ON_VSEL, PLDO2_ON_VSEL, PLDO3_ON_VSEL, PLDO4_ON_VSEL, PLDO5_ON_VSEL, 440 PLDO6_ON_VSEL, 441 PLDO1_SLP_VSEL, PLDO2_SLP_VSEL, PLDO3_SLP_VSEL, PLDO4_SLP_VSEL, PLDO5_SLP_VSEL, 442 PLDO6_SLP_VSEL, 443 BUCK1_RATE, BUCK2_RATE, BUCK3_RATE, BUCK4_RATE, BUCK5_RATE, BUCK6_RATE, 444 BUCK7_RATE, BUCK8_RATE, BUCK9_RATE, BUCK10_RATE, 445 PWRON_STS, VDC_STS, VB_UV_STSS, VB_LO_STS, HOTDIE_STS, TSD_STS, VB_OV_STS, 446 VB_UV_DLY, VB_UV_SEL, VB_LO_ACT, VB_LO_SEL, 447 ABNORDET_EN, TSD_TEMP, HOTDIE_TMP, SYS_OV_SD_EN, SYS_OV_SD_DLY_SEL, DLY_ABN_SHORT, 448 VCCXDET_DIS, OSC_TC, ENB2_2M, ENB_32K, 449 PWRCTRL1_FUN, PWRCTRL2_FUN, PWRCTRL3_FUN, 450 PWRCTRL1_POL, PWRCTRL2_POL, PWRCTRL3_POL, 451 BUCK1_VSEL_CTR_SEL, BUCK2_VSEL_CTR_SEL, BUCK3_VSEL_CTR_SEL, BUCK4_VSEL_CTR_SEL, 452 BUCK5_VSEL_CTR_SEL, BUCK6_VSEL_CTR_SEL, BUCK7_VSEL_CTR_SEL, BUCK8_VSEL_CTR_SEL, 453 BUCK9_VSEL_CTR_SEL, BUCK10_VSEL_CTR_SEL, 454 NLDO1_VSEL_CTR_SEL, NLDO2_VSEL_CTR_SEL, NLDO3_VSEL_CTR_SEL, NLDO4_VSEL_CTR_SEL, 455 NLDO5_VSEL_CTR_SEL, 456 PLDO1_VSEL_CTR_SEL, PLDO2_VSEL_CTR_SEL, PLDO3_VSEL_CTR_SEL, PLDO4_VSEL_CTR_SEL, 457 PLDO5_VSEL_CTR_SEL, PLDO6_VSEL_CTR_SEL, 458 BUCK1_DVS_CTR_SEL, BUCK2_DVS_CTR_SEL, BUCK3_DVS_CTR_SEL, BUCK4_DVS_CTR_SEL, 459 BUCK5_DVS_CTR_SEL, BUCK6_DVS_CTR_SEL, BUCK7_DVS_CTR_SEL, BUCK8_DVS_CTR_SEL, 460 BUCK9_DVS_CTR_SEL, BUCK10_DVS_CTR_SEL, 461 NLDO1_DVS_CTR_SEL, NLDO2_DVS_CTR_SEL, NLDO3_DVS_CTR_SEL, NLDO4_DVS_CTR_SEL, 462 NLDO5_DVS_CTR_SEL, 463 PLDO1_DVS_CTR_SEL, PLDO2_DVS_CTR_SEL, PLDO3_DVS_CTR_SEL, PLDO4_DVS_CTR_SEL, 464 PLDO5_DVS_CTR_SEL, PLDO6_DVS_CTR_SEL, 465 DVS_START1, DVS_START2, DVS_START3, 466 SLP3_DATA, SLP2_DATA, SLP1_DATA, SLP3_DR, SLP2_DR, SLP1_DR, 467 468 RST_FUN, DEV_RST, DEV_SLP, SLAVE_RESTART_FUN, DEV_OFF, 469 WDT_CLR, WDT_EN, WDT_SET, ON_SOURCE, OFF_SOURCE, 470 ON_PWRON, ON_VDC, RESTART_RESETB, RESTART_PWRON_LP, RESTART_SLP, 471 RESTART_DEV_RST, RESTART_WDT, 472 OFF_SLP, VB_SYS_OV, OFF_TSD, OFF_DEV_OFF, OFF_PWRON_LP, OFF_VB_LO, 473 PWRON_ON_TIME, PWRON_LP_ACT, PWRON_LP_OFF_TIME, PWRON_LP_TM_SEL, PWRON_DB_SEL, 474 VB_LO_INT, VDC_FALL_INT, VDC_RISE_INT, HOTDIE_INT, PWRON_LP_INT, PWRON_INT, 475 PWRON_RISE_INT, PWRON_FALL_INT, 476 VB_LO_IM, VDC_FALL_INT_IM, VDC_RISE_IM, HOTDIE_IM, PWRON_LP_IM, 477 PWRON_IM, PWRON_RISE_INT_IM, PWRON_FALL_INT_IM, 478 WDT_INT, SLP1_GPIO_INT, SLP2_GPIO_INT, SLP3_GPIO_INT, 479 WDT_INT_IM, SLP1_GPIO_IM, SLP2_GPIO_IM, SLP3_GPIO_IM, 480 INT_FUNCTION, INT_POL, INT_FC_EN, 481 LDO_RATE, BUCK1_RATE2, BUCK2_RATE2, BUCK3_RATE2, BUCK4_RATE2, 482 BUCK5_RATE2, BUCK6_RATE2, BUCK7_RATE2, BUCK8_RATE2, BUCK9_RATE2, 483 BUCK10_RATE2, 484 F_MAX_FIELDS 485 }; 486 487 struct rk806_platform_data { 488 int low_voltage_threshold; 489 int shutdown_voltage_threshold; 490 int force_shutdown_enable; 491 int shutdown_temperture_threshold; 492 int hotdie_temperture_threshold; 493 }; 494 495 struct rk806_pin_info { 496 struct pinctrl *p; 497 struct pinctrl_state *default_st; 498 struct pinctrl_state *power_off; 499 struct pinctrl_state *reset; 500 struct pinctrl_state *sleep; 501 struct pinctrl_state *dvs; 502 }; 503 504 /* 505 * struct rk806 - state holder for the rk806 driver 506 * 507 * Device data may be used to access the rk806 chip 508 */ 509 struct rk806 { 510 struct device *dev; 511 struct regmap *regmap; 512 struct regmap_field *rmap_fields[F_MAX_FIELDS]; 513 /* IRQ Data */ 514 int irq; 515 struct regmap_irq_chip_data *irq_data; 516 struct rk806_platform_data *pdata; 517 struct rk806_pin_info *pins; 518 int vb_lo_irq; 519 }; 520 521 extern const struct regmap_config rk806_regmap_config_spi; 522 int rk806_device_init(struct rk806 *rk806); 523 int rk806_device_exit(struct rk806 *rk806); 524 int rk806_field_write(struct rk806 *rk806, 525 enum rk806_fields field_id, 526 unsigned int val); 527 int rk806_field_read(struct rk806 *rk806, 528 enum rk806_fields field_id); 529 #endif /* __LINUX_REGULATOR_RK806_H */ 530