1/* 2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without modification, 6 * are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, this list of 9 * conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, this list 12 * of conditions and the following disclaimer in the documentation and/or other materials 13 * provided with the distribution. 14 * 15 * 3. Neither the name of the copyright holder nor the names of its contributors may be used 16 * to endorse or promote products derived from this software without specific prior written 17 * permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 33#include "asm.h" 34 35 .fpu vfpv4 36 .arch armv7a 37.macro DCACHE_LINE_SIZE, reg, tmp 38 mrc p15, 0, \tmp, c0, c0, 1 39 lsr \tmp, \tmp, #16 40 and \tmp, \tmp, #0xf 41 mov \reg, #4 42 mov \reg, \reg, lsl \tmp 43.endm 44 45 46FUNCTION(arm_inv_cache_range) 47 push {r2, r3} 48 DCACHE_LINE_SIZE r2, r3 49 sub r3, r2, #1 50 tst r0, r3 51 bic r0, r0, r3 52 53 mcrne p15, 0, r0, c7, c14, 1 54 55 tst r1, r3 56 bic r1, r1, r3 57 mcrne p15, 0, r1, c7, c14, 1 581: 59 mcr p15, 0, r0, c7, c6, 1 60 add r0, r0, r2 61 cmp r0, r1 62 blo 1b 63 dsb 64 pop {r2, r3} 65 mov pc, lr 66 67FUNCTION(arm_clean_cache_range) 68 push {r2, r3} 69 DCACHE_LINE_SIZE r2, r3 70 sub r3, r2, #1 71 bic r0, r0, r3 72 731: 74 mcr p15, 0, r0, c7, c10, 1 75 add r0, r0, r2 76 cmp r0, r1 77 blo 1b 78 dsb 79 pop {r2, r3} 80 mov pc, lr 81