// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2020, The Linux Foundation. All rights reserved. */ #include #include #include #include #include #include #include #include #include #include / { interrupt-parent = <&intc>; #address-cells = <2>; #size-cells = <2>; aliases { i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; i2c3 = &i2c3; i2c4 = &i2c4; i2c5 = &i2c5; i2c6 = &i2c6; i2c7 = &i2c7; i2c8 = &i2c8; i2c9 = &i2c9; i2c10 = &i2c10; i2c11 = &i2c11; i2c12 = &i2c12; i2c13 = &i2c13; i2c14 = &i2c14; i2c15 = &i2c15; i2c16 = &i2c16; i2c17 = &i2c17; i2c18 = &i2c18; i2c19 = &i2c19; spi0 = &spi0; spi1 = &spi1; spi2 = &spi2; spi3 = &spi3; spi4 = &spi4; spi5 = &spi5; spi6 = &spi6; spi7 = &spi7; spi8 = &spi8; spi9 = &spi9; spi10 = &spi10; spi11 = &spi11; spi12 = &spi12; spi13 = &spi13; spi14 = &spi14; spi15 = &spi15; spi16 = &spi16; spi17 = &spi17; spi18 = &spi18; spi19 = &spi19; }; chosen { }; clocks { xo_board: xo-board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <38400000>; clock-output-names = "xo_board"; }; sleep_clk: sleep-clk { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; }; }; cpus { #address-cells = <2>; #size-cells = <0>; CPU0: cpu@0 { device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; L3_0: l3-cache { compatible = "cache"; }; }; }; CPU1: cpu@100 { device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x100>; enable-method = "psci"; next-level-cache = <&L2_100>; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; }; }; CPU2: cpu@200 { device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x200>; enable-method = "psci"; next-level-cache = <&L2_200>; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; }; }; CPU3: cpu@300 { device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x300>; enable-method = "psci"; next-level-cache = <&L2_300>; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; }; }; CPU4: cpu@400 { device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x400>; enable-method = "psci"; next-level-cache = <&L2_400>; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; }; }; CPU5: cpu@500 { device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x500>; enable-method = "psci"; next-level-cache = <&L2_500>; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; }; }; CPU6: cpu@600 { device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x600>; enable-method = "psci"; next-level-cache = <&L2_600>; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; }; }; CPU7: cpu@700 { device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x700>; enable-method = "psci"; next-level-cache = <&L2_700>; qcom,freq-domain = <&cpufreq_hw 2>; #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; }; }; }; firmware { scm: scm { compatible = "qcom,scm"; #reset-cells = <1>; }; }; memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the size */ reg = <0x0 0x80000000 0x0 0x0>; }; pmu { compatible = "arm,armv8-pmuv3"; interrupts = ; }; psci { compatible = "arm,psci-1.0"; method = "smc"; }; reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; hyp_mem: memory@80000000 { reg = <0x0 0x80000000 0x0 0x600000>; no-map; }; xbl_aop_mem: memory@80700000 { reg = <0x0 0x80700000 0x0 0x160000>; no-map; }; cmd_db: memory@80860000 { compatible = "qcom,cmd-db"; reg = <0x0 0x80860000 0x0 0x20000>; no-map; }; smem_mem: memory@80900000 { reg = <0x0 0x80900000 0x0 0x200000>; no-map; }; removed_mem: memory@80b00000 { reg = <0x0 0x80b00000 0x0 0x5300000>; no-map; }; camera_mem: memory@86200000 { reg = <0x0 0x86200000 0x0 0x500000>; no-map; }; wlan_mem: memory@86700000 { reg = <0x0 0x86700000 0x0 0x100000>; no-map; }; ipa_fw_mem: memory@86800000 { reg = <0x0 0x86800000 0x0 0x10000>; no-map; }; ipa_gsi_mem: memory@86810000 { reg = <0x0 0x86810000 0x0 0xa000>; no-map; }; gpu_mem: memory@8681a000 { reg = <0x0 0x8681a000 0x0 0x2000>; no-map; }; npu_mem: memory@86900000 { reg = <0x0 0x86900000 0x0 0x500000>; no-map; }; video_mem: memory@86e00000 { reg = <0x0 0x86e00000 0x0 0x500000>; no-map; }; cvp_mem: memory@87300000 { reg = <0x0 0x87300000 0x0 0x500000>; no-map; }; cdsp_mem: memory@87800000 { reg = <0x0 0x87800000 0x0 0x1400000>; no-map; }; slpi_mem: memory@88c00000 { reg = <0x0 0x88c00000 0x0 0x1500000>; no-map; }; adsp_mem: memory@8a100000 { reg = <0x0 0x8a100000 0x0 0x1d00000>; no-map; }; spss_mem: memory@8be00000 { reg = <0x0 0x8be00000 0x0 0x100000>; no-map; }; cdsp_secure_heap: memory@8bf00000 { reg = <0x0 0x8bf00000 0x0 0x4600000>; no-map; }; }; smem: qcom,smem { compatible = "qcom,smem"; memory-region = <&smem_mem>; hwlocks = <&tcsr_mutex 3>; }; smp2p-adsp { compatible = "qcom,smp2p"; qcom,smem = <443>, <429>; interrupts-extended = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P>; qcom,local-pid = <0>; qcom,remote-pid = <2>; smp2p_adsp_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; smp2p_adsp_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; }; smp2p-cdsp { compatible = "qcom,smp2p"; qcom,smem = <94>, <432>; interrupts-extended = <&ipcc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>; qcom,local-pid = <0>; qcom,remote-pid = <5>; smp2p_cdsp_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; smp2p_cdsp_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; }; smp2p-slpi { compatible = "qcom,smp2p"; qcom,smem = <481>, <430>; interrupts-extended = <&ipcc IPCC_CLIENT_SLPI IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_SLPI IPCC_MPROC_SIGNAL_SMP2P>; qcom,local-pid = <0>; qcom,remote-pid = <3>; smp2p_slpi_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; smp2p_slpi_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; }; soc: soc@0 { #address-cells = <2>; #size-cells = <2>; ranges = <0 0 0 0 0x10 0>; dma-ranges = <0 0 0 0 0x10 0>; compatible = "simple-bus"; gcc: clock-controller@100000 { compatible = "qcom,gcc-sm8250"; reg = <0x0 0x00100000 0x0 0x1f0000>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; }; ipcc: mailbox@408000 { compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; reg = <0 0x00408000 0 0x1000>; interrupts = ; interrupt-controller; #interrupt-cells = <3>; #mbox-cells = <2>; }; qup_opp_table: qup-opp-table { compatible = "operating-points-v2"; opp-50000000 { opp-hz = /bits/ 64 <50000000>; required-opps = <&rpmhpd_opp_min_svs>; }; opp-75000000 { opp-hz = /bits/ 64 <75000000>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-120000000 { opp-hz = /bits/ 64 <120000000>; required-opps = <&rpmhpd_opp_svs>; }; }; qupv3_id_2: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x008c0000 0x0 0x6000>; clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; #address-cells = <2>; #size-cells = <2>; ranges; status = "disabled"; i2c14: i2c@880000 { compatible = "qcom,geni-i2c"; reg = <0 0x00880000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c14_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi14: spi@880000 { compatible = "qcom,geni-spi"; reg = <0 0x00880000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi14_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; i2c15: i2c@884000 { compatible = "qcom,geni-i2c"; reg = <0 0x00884000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c15_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi15: spi@884000 { compatible = "qcom,geni-spi"; reg = <0 0x00884000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi15_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; i2c16: i2c@888000 { compatible = "qcom,geni-i2c"; reg = <0 0x00888000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c16_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi16: spi@888000 { compatible = "qcom,geni-spi"; reg = <0 0x00888000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi16_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; i2c17: i2c@88c000 { compatible = "qcom,geni-i2c"; reg = <0 0x0088c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c17_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi17: spi@88c000 { compatible = "qcom,geni-spi"; reg = <0 0x0088c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi17_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; uart17: serial@88c000 { compatible = "qcom,geni-uart"; reg = <0 0x0088c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_uart17_default>; interrupts = ; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; i2c18: i2c@890000 { compatible = "qcom,geni-i2c"; reg = <0 0x00890000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c18_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi18: spi@890000 { compatible = "qcom,geni-spi"; reg = <0 0x00890000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi18_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; uart18: serial@890000 { compatible = "qcom,geni-uart"; reg = <0 0x00890000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_uart18_default>; interrupts = ; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; i2c19: i2c@894000 { compatible = "qcom,geni-i2c"; reg = <0 0x00894000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c19_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi19: spi@894000 { compatible = "qcom,geni-spi"; reg = <0 0x00894000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi19_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; }; qupv3_id_0: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x009c0000 0x0 0x6000>; clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; #address-cells = <2>; #size-cells = <2>; ranges; status = "disabled"; i2c0: i2c@980000 { compatible = "qcom,geni-i2c"; reg = <0 0x00980000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c0_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi0: spi@980000 { compatible = "qcom,geni-spi"; reg = <0 0x00980000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi0_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; i2c1: i2c@984000 { compatible = "qcom,geni-i2c"; reg = <0 0x00984000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c1_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi1: spi@984000 { compatible = "qcom,geni-spi"; reg = <0 0x00984000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi1_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; i2c2: i2c@988000 { compatible = "qcom,geni-i2c"; reg = <0 0x00988000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c2_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi2: spi@988000 { compatible = "qcom,geni-spi"; reg = <0 0x00988000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi2_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; uart2: serial@988000 { compatible = "qcom,geni-debug-uart"; reg = <0 0x00988000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_uart2_default>; interrupts = ; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; i2c3: i2c@98c000 { compatible = "qcom,geni-i2c"; reg = <0 0x0098c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c3_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi3: spi@98c000 { compatible = "qcom,geni-spi"; reg = <0 0x0098c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi3_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; i2c4: i2c@990000 { compatible = "qcom,geni-i2c"; reg = <0 0x00990000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c4_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi4: spi@990000 { compatible = "qcom,geni-spi"; reg = <0 0x00990000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi4_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; i2c5: i2c@994000 { compatible = "qcom,geni-i2c"; reg = <0 0x00994000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c5_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi5: spi@994000 { compatible = "qcom,geni-spi"; reg = <0 0x00994000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi5_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; i2c6: i2c@998000 { compatible = "qcom,geni-i2c"; reg = <0 0x00998000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c6_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi6: spi@998000 { compatible = "qcom,geni-spi"; reg = <0 0x00998000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi6_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; uart6: serial@998000 { compatible = "qcom,geni-uart"; reg = <0 0x00998000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_uart6_default>; interrupts = ; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; i2c7: i2c@99c000 { compatible = "qcom,geni-i2c"; reg = <0 0x0099c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c7_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi7: spi@99c000 { compatible = "qcom,geni-spi"; reg = <0 0x0099c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi7_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; }; qupv3_id_1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x00ac0000 0x0 0x6000>; clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; #address-cells = <2>; #size-cells = <2>; ranges; status = "disabled"; i2c8: i2c@a80000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a80000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c8_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi8: spi@a80000 { compatible = "qcom,geni-spi"; reg = <0 0x00a80000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi8_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; i2c9: i2c@a84000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a84000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c9_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi9: spi@a84000 { compatible = "qcom,geni-spi"; reg = <0 0x00a84000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi9_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; i2c10: i2c@a88000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a88000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c10_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi10: spi@a88000 { compatible = "qcom,geni-spi"; reg = <0 0x00a88000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi10_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; i2c11: i2c@a8c000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a8c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c11_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi11: spi@a8c000 { compatible = "qcom,geni-spi"; reg = <0 0x00a8c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi11_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; i2c12: i2c@a90000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a90000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c12_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi12: spi@a90000 { compatible = "qcom,geni-spi"; reg = <0 0x00a90000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi12_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; uart12: serial@a90000 { compatible = "qcom,geni-debug-uart"; reg = <0x0 0x00a90000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_uart12_default>; interrupts = ; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; i2c13: i2c@a94000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a94000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c13_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi13: spi@a94000 { compatible = "qcom,geni-spi"; reg = <0 0x00a94000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi13_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; }; config_noc: interconnect@1500000 { compatible = "qcom,sm8250-config-noc"; reg = <0 0x01500000 0 0xa580>; #interconnect-cells = <1>; qcom,bcm-voters = <&apps_bcm_voter>; }; system_noc: interconnect@1620000 { compatible = "qcom,sm8250-system-noc"; reg = <0 0x01620000 0 0x1c200>; #interconnect-cells = <1>; qcom,bcm-voters = <&apps_bcm_voter>; }; mc_virt: interconnect@163d000 { compatible = "qcom,sm8250-mc-virt"; reg = <0 0x0163d000 0 0x1000>; #interconnect-cells = <1>; qcom,bcm-voters = <&apps_bcm_voter>; }; aggre1_noc: interconnect@16e0000 { compatible = "qcom,sm8250-aggre1-noc"; reg = <0 0x016e0000 0 0x1f180>; #interconnect-cells = <1>; qcom,bcm-voters = <&apps_bcm_voter>; }; aggre2_noc: interconnect@1700000 { compatible = "qcom,sm8250-aggre2-noc"; reg = <0 0x01700000 0 0x33000>; #interconnect-cells = <1>; qcom,bcm-voters = <&apps_bcm_voter>; }; compute_noc: interconnect@1733000 { compatible = "qcom,sm8250-compute-noc"; reg = <0 0x01733000 0 0xa180>; #interconnect-cells = <1>; qcom,bcm-voters = <&apps_bcm_voter>; }; mmss_noc: interconnect@1740000 { compatible = "qcom,sm8250-mmss-noc"; reg = <0 0x01740000 0 0x1f080>; #interconnect-cells = <1>; qcom,bcm-voters = <&apps_bcm_voter>; }; ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sm8250-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg = <0 0x01d84000 0 0x3000>; interrupts = ; phys = <&ufs_mem_phy_lanes>; phy-names = "ufsphy"; lanes-per-direction = <2>; #reset-cells = <1>; resets = <&gcc GCC_UFS_PHY_BCR>; reset-names = "rst"; power-domains = <&gcc UFS_PHY_GDSC>; clock-names = "core_clk", "bus_aggr_clk", "iface_clk", "core_clk_unipro", "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk", "rx_lane1_sync_clk"; clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, <&gcc GCC_UFS_PHY_AHB_CLK>, <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; freq-table-hz = <37500000 300000000>, <0 0>, <0 0>, <37500000 300000000>, <0 0>, <0 0>, <0 0>, <0 0>; status = "disabled"; }; ufs_mem_phy: phy@1d87000 { compatible = "qcom,sm8250-qmp-ufs-phy"; reg = <0 0x01d87000 0 0x1c0>; #address-cells = <2>; #size-cells = <2>; ranges; clock-names = "ref", "ref_aux"; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; status = "disabled"; ufs_mem_phy_lanes: lanes@1d87400 { reg = <0 0x01d87400 0 0x108>, <0 0x01d87600 0 0x1e0>, <0 0x01d87c00 0 0x1dc>, <0 0x01d87800 0 0x108>, <0 0x01d87a00 0 0x1e0>; #phy-cells = <0>; }; }; ipa_virt: interconnect@1e00000 { compatible = "qcom,sm8250-ipa-virt"; reg = <0 0x01e00000 0 0x1000>; #interconnect-cells = <1>; qcom,bcm-voters = <&apps_bcm_voter>; }; tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>; #hwlock-cells = <1>; }; gpu: gpu@3d00000 { /* * note: the amd,imageon compatible makes it possible * to use the drm/msm driver without the display node, * make sure to remove it when display node is added */ compatible = "qcom,adreno-650.2", "qcom,adreno", "amd,imageon"; #stream-id-cells = <16>; reg = <0 0x03d00000 0 0x40000>; reg-names = "kgsl_3d0_reg_memory"; interrupts = ; iommus = <&adreno_smmu 0 0x401>; operating-points-v2 = <&gpu_opp_table>; qcom,gmu = <&gmu>; zap-shader { memory-region = <&gpu_mem>; }; /* note: downstream checks gpu binning for 670 Mhz */ gpu_opp_table: opp-table { compatible = "operating-points-v2"; opp-670000000 { opp-hz = /bits/ 64 <670000000>; opp-level = ; }; opp-587000000 { opp-hz = /bits/ 64 <587000000>; opp-level = ; }; opp-525000000 { opp-hz = /bits/ 64 <525000000>; opp-level = ; }; opp-490000000 { opp-hz = /bits/ 64 <490000000>; opp-level = ; }; opp-441600000 { opp-hz = /bits/ 64 <441600000>; opp-level = ; }; opp-400000000 { opp-hz = /bits/ 64 <400000000>; opp-level = ; }; opp-305000000 { opp-hz = /bits/ 64 <305000000>; opp-level = ; }; }; }; gmu: gmu@3d6a000 { compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; reg = <0 0x03d6a000 0 0x30000>, <0 0x3de0000 0 0x10000>, <0 0xb290000 0 0x10000>, <0 0xb490000 0 0x10000>; reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq"; interrupts = , ; interrupt-names = "hfi", "gmu"; clocks = <&gpucc GPU_CC_AHB_CLK>, <&gpucc GPU_CC_CX_GMU_CLK>, <&gpucc GPU_CC_CXO_CLK>, <&gcc GCC_DDRSS_GPU_AXI_CLK>, <&gcc GCC_GPU_MEMNOC_GFX_CLK>; clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; power-domains = <&gpucc GPU_CX_GDSC>, <&gpucc GPU_GX_GDSC>; power-domain-names = "cx", "gx"; iommus = <&adreno_smmu 5 0x400>; operating-points-v2 = <&gmu_opp_table>; gmu_opp_table: opp-table { compatible = "operating-points-v2"; opp-200000000 { opp-hz = /bits/ 64 <200000000>; opp-level = ; }; }; }; gpucc: clock-controller@3d90000 { compatible = "qcom,sm8250-gpucc"; reg = <0 0x03d90000 0 0x9000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPU_GPLL0_CLK_SRC>, <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; clock-names = "bi_tcxo", "gcc_gpu_gpll0_clk_src", "gcc_gpu_gpll0_div_clk_src"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; }; adreno_smmu: iommu@3da0000 { compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; reg = <0 0x03da0000 0 0x10000>; #iommu-cells = <2>; #global-interrupts = <2>; interrupts = , , , , , , , , , ; clocks = <&gpucc GPU_CC_AHB_CLK>, <&gcc GCC_GPU_MEMNOC_GFX_CLK>, <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; clock-names = "ahb", "bus", "iface"; power-domains = <&gpucc GPU_CX_GDSC>; }; slpi: remoteproc@5c00000 { compatible = "qcom,sm8250-slpi-pas"; reg = <0 0x05c00000 0 0x4000>; interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>, <&rpmhpd SM8250_LCX>, <&rpmhpd SM8250_LMX>; power-domain-names = "load_state", "lcx", "lmx"; memory-region = <&slpi_mem>; qcom,smem-states = <&smp2p_slpi_out 0>; qcom,smem-state-names = "stop"; status = "disabled"; glink-edge { interrupts-extended = <&ipcc IPCC_CLIENT_SLPI IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_SLPI IPCC_MPROC_SIGNAL_GLINK_QMP>; label = "lpass"; qcom,remote-pid = <3>; }; }; cdsp: remoteproc@8300000 { compatible = "qcom,sm8250-cdsp-pas"; reg = <0 0x08300000 0 0x10000>; interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>, <&rpmhpd SM8250_CX>; power-domain-names = "load_state", "cx"; memory-region = <&cdsp_mem>; qcom,smem-states = <&smp2p_cdsp_out 0>; qcom,smem-state-names = "stop"; status = "disabled"; glink-edge { interrupts-extended = <&ipcc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_GLINK_QMP>; label = "lpass"; qcom,remote-pid = <5>; }; }; dc_noc: interconnect@90c0000 { compatible = "qcom,sm8250-dc-noc"; reg = <0 0x090c0000 0 0x4200>; #interconnect-cells = <1>; qcom,bcm-voters = <&apps_bcm_voter>; }; gem_noc: interconnect@9100000 { compatible = "qcom,sm8250-gem-noc"; reg = <0 0x09100000 0 0xb4000>; #interconnect-cells = <1>; qcom,bcm-voters = <&apps_bcm_voter>; }; npu_noc: interconnect@9990000 { compatible = "qcom,sm8250-npu-noc"; reg = <0 0x09990000 0 0x1600>; #interconnect-cells = <1>; qcom,bcm-voters = <&apps_bcm_voter>; }; pdc: interrupt-controller@b220000 { compatible = "qcom,sm8250-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>, <126 716 12>; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupt-controller; }; tsens0: thermal-sensor@c263000 { compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; reg = <0 0x0c263000 0 0x1ff>, /* TM */ <0 0x0c222000 0 0x1ff>; /* SROT */ #qcom,sensors = <16>; interrupts = , ; interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <1>; }; tsens1: thermal-sensor@c265000 { compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; reg = <0 0x0c265000 0 0x1ff>, /* TM */ <0 0x0c223000 0 0x1ff>; /* SROT */ #qcom,sensors = <9>; interrupts = , ; interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <1>; }; aoss_qmp: qmp@c300000 { compatible = "qcom,sm8250-aoss-qmp"; reg = <0 0x0c300000 0 0x100000>; interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; #clock-cells = <0>; #power-domain-cells = <1>; }; spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x0 0x0c440000 0x0 0x0001100>, <0x0 0x0c600000 0x0 0x2000000>, <0x0 0x0e600000 0x0 0x0100000>, <0x0 0x0e700000 0x0 0x00a0000>, <0x0 0x0c40a000 0x0 0x0026000>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; qcom,ee = <0>; qcom,channel = <0>; #address-cells = <2>; #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; }; tlmm: pinctrl@f100000 { compatible = "qcom,sm8250-pinctrl"; reg = <0 0x0f100000 0 0x300000>, <0 0x0f500000 0 0x300000>, <0 0x0f900000 0 0x300000>; reg-names = "west", "south", "north"; interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&tlmm 0 0 181>; wakeup-parent = <&pdc>; qup_i2c0_default: qup-i2c0-default { mux { pins = "gpio28", "gpio29"; function = "qup0"; }; config { pins = "gpio28", "gpio29"; drive-strength = <2>; bias-disable; }; }; qup_i2c1_default: qup-i2c1-default { pinmux { pins = "gpio4", "gpio5"; function = "qup1"; }; config { pins = "gpio4", "gpio5"; drive-strength = <2>; bias-disable; }; }; qup_i2c2_default: qup-i2c2-default { mux { pins = "gpio115", "gpio116"; function = "qup2"; }; config { pins = "gpio115", "gpio116"; drive-strength = <2>; bias-disable; }; }; qup_i2c3_default: qup-i2c3-default { mux { pins = "gpio119", "gpio120"; function = "qup3"; }; config { pins = "gpio119", "gpio120"; drive-strength = <2>; bias-disable; }; }; qup_i2c4_default: qup-i2c4-default { mux { pins = "gpio8", "gpio9"; function = "qup4"; }; config { pins = "gpio8", "gpio9"; drive-strength = <2>; bias-disable; }; }; qup_i2c5_default: qup-i2c5-default { mux { pins = "gpio12", "gpio13"; function = "qup5"; }; config { pins = "gpio12", "gpio13"; drive-strength = <2>; bias-disable; }; }; qup_i2c6_default: qup-i2c6-default { mux { pins = "gpio16", "gpio17"; function = "qup6"; }; config { pins = "gpio16", "gpio17"; drive-strength = <2>; bias-disable; }; }; qup_i2c7_default: qup-i2c7-default { mux { pins = "gpio20", "gpio21"; function = "qup7"; }; config { pins = "gpio20", "gpio21"; drive-strength = <2>; bias-disable; }; }; qup_i2c8_default: qup-i2c8-default { mux { pins = "gpio24", "gpio25"; function = "qup8"; }; config { pins = "gpio24", "gpio25"; drive-strength = <2>; bias-disable; }; }; qup_i2c9_default: qup-i2c9-default { mux { pins = "gpio125", "gpio126"; function = "qup9"; }; config { pins = "gpio125", "gpio126"; drive-strength = <2>; bias-disable; }; }; qup_i2c10_default: qup-i2c10-default { mux { pins = "gpio129", "gpio130"; function = "qup10"; }; config { pins = "gpio129", "gpio130"; drive-strength = <2>; bias-disable; }; }; qup_i2c11_default: qup-i2c11-default { mux { pins = "gpio60", "gpio61"; function = "qup11"; }; config { pins = "gpio60", "gpio61"; drive-strength = <2>; bias-disable; }; }; qup_i2c12_default: qup-i2c12-default { mux { pins = "gpio32", "gpio33"; function = "qup12"; }; config { pins = "gpio32", "gpio33"; drive-strength = <2>; bias-disable; }; }; qup_i2c13_default: qup-i2c13-default { mux { pins = "gpio36", "gpio37"; function = "qup13"; }; config { pins = "gpio36", "gpio37"; drive-strength = <2>; bias-disable; }; }; qup_i2c14_default: qup-i2c14-default { mux { pins = "gpio40", "gpio41"; function = "qup14"; }; config { pins = "gpio40", "gpio41"; drive-strength = <2>; bias-disable; }; }; qup_i2c15_default: qup-i2c15-default { mux { pins = "gpio44", "gpio45"; function = "qup15"; }; config { pins = "gpio44", "gpio45"; drive-strength = <2>; bias-disable; }; }; qup_i2c16_default: qup-i2c16-default { mux { pins = "gpio48", "gpio49"; function = "qup16"; }; config { pins = "gpio48", "gpio49"; drive-strength = <2>; bias-disable; }; }; qup_i2c17_default: qup-i2c17-default { mux { pins = "gpio52", "gpio53"; function = "qup17"; }; config { pins = "gpio52", "gpio53"; drive-strength = <2>; bias-disable; }; }; qup_i2c18_default: qup-i2c18-default { mux { pins = "gpio56", "gpio57"; function = "qup18"; }; config { pins = "gpio56", "gpio57"; drive-strength = <2>; bias-disable; }; }; qup_i2c19_default: qup-i2c19-default { mux { pins = "gpio0", "gpio1"; function = "qup19"; }; config { pins = "gpio0", "gpio1"; drive-strength = <2>; bias-disable; }; }; qup_spi0_default: qup-spi0-default { mux { pins = "gpio28", "gpio29", "gpio30", "gpio31"; function = "qup0"; }; config { pins = "gpio28", "gpio29", "gpio30", "gpio31"; drive-strength = <6>; bias-disable; }; }; qup_spi1_default: qup-spi1-default { mux { pins = "gpio4", "gpio5", "gpio6", "gpio7"; function = "qup1"; }; config { pins = "gpio4", "gpio5", "gpio6", "gpio7"; drive-strength = <6>; bias-disable; }; }; qup_spi2_default: qup-spi2-default { mux { pins = "gpio115", "gpio116", "gpio117", "gpio118"; function = "qup2"; }; config { pins = "gpio115", "gpio116", "gpio117", "gpio118"; drive-strength = <6>; bias-disable; }; }; qup_spi3_default: qup-spi3-default { mux { pins = "gpio119", "gpio120", "gpio121", "gpio122"; function = "qup3"; }; config { pins = "gpio119", "gpio120", "gpio121", "gpio122"; drive-strength = <6>; bias-disable; }; }; qup_spi4_default: qup-spi4-default { mux { pins = "gpio8", "gpio9", "gpio10", "gpio11"; function = "qup4"; }; config { pins = "gpio8", "gpio9", "gpio10", "gpio11"; drive-strength = <6>; bias-disable; }; }; qup_spi5_default: qup-spi5-default { mux { pins = "gpio12", "gpio13", "gpio14", "gpio15"; function = "qup5"; }; config { pins = "gpio12", "gpio13", "gpio14", "gpio15"; drive-strength = <6>; bias-disable; }; }; qup_spi6_default: qup-spi6-default { mux { pins = "gpio16", "gpio17", "gpio18", "gpio19"; function = "qup6"; }; config { pins = "gpio16", "gpio17", "gpio18", "gpio19"; drive-strength = <6>; bias-disable; }; }; qup_spi7_default: qup-spi7-default { mux { pins = "gpio20", "gpio21", "gpio22", "gpio23"; function = "qup7"; }; config { pins = "gpio20", "gpio21", "gpio22", "gpio23"; drive-strength = <6>; bias-disable; }; }; qup_spi8_default: qup-spi8-default { mux { pins = "gpio24", "gpio25", "gpio26", "gpio27"; function = "qup8"; }; config { pins = "gpio24", "gpio25", "gpio26", "gpio27"; drive-strength = <6>; bias-disable; }; }; qup_spi9_default: qup-spi9-default { mux { pins = "gpio125", "gpio126", "gpio127", "gpio128"; function = "qup9"; }; config { pins = "gpio125", "gpio126", "gpio127", "gpio128"; drive-strength = <6>; bias-disable; }; }; qup_spi10_default: qup-spi10-default { mux { pins = "gpio129", "gpio130", "gpio131", "gpio132"; function = "qup10"; }; config { pins = "gpio129", "gpio130", "gpio131", "gpio132"; drive-strength = <6>; bias-disable; }; }; qup_spi11_default: qup-spi11-default { mux { pins = "gpio60", "gpio61", "gpio62", "gpio63"; function = "qup11"; }; config { pins = "gpio60", "gpio61", "gpio62", "gpio63"; drive-strength = <6>; bias-disable; }; }; qup_spi12_default: qup-spi12-default { mux { pins = "gpio32", "gpio33", "gpio34", "gpio35"; function = "qup12"; }; config { pins = "gpio32", "gpio33", "gpio34", "gpio35"; drive-strength = <6>; bias-disable; }; }; qup_spi13_default: qup-spi13-default { mux { pins = "gpio36", "gpio37", "gpio38", "gpio39"; function = "qup13"; }; config { pins = "gpio36", "gpio37", "gpio38", "gpio39"; drive-strength = <6>; bias-disable; }; }; qup_spi14_default: qup-spi14-default { mux { pins = "gpio40", "gpio41", "gpio42", "gpio43"; function = "qup14"; }; config { pins = "gpio40", "gpio41", "gpio42", "gpio43"; drive-strength = <6>; bias-disable; }; }; qup_spi15_default: qup-spi15-default { mux { pins = "gpio44", "gpio45", "gpio46", "gpio47"; function = "qup15"; }; config { pins = "gpio44", "gpio45", "gpio46", "gpio47"; drive-strength = <6>; bias-disable; }; }; qup_spi16_default: qup-spi16-default { mux { pins = "gpio48", "gpio49", "gpio50", "gpio51"; function = "qup16"; }; config { pins = "gpio48", "gpio49", "gpio50", "gpio51"; drive-strength = <6>; bias-disable; }; }; qup_spi17_default: qup-spi17-default { mux { pins = "gpio52", "gpio53", "gpio54", "gpio55"; function = "qup17"; }; config { pins = "gpio52", "gpio53", "gpio54", "gpio55"; drive-strength = <6>; bias-disable; }; }; qup_spi18_default: qup-spi18-default { mux { pins = "gpio56", "gpio57", "gpio58", "gpio59"; function = "qup18"; }; config { pins = "gpio56", "gpio57", "gpio58", "gpio59"; drive-strength = <6>; bias-disable; }; }; qup_spi19_default: qup-spi19-default { mux { pins = "gpio0", "gpio1", "gpio2", "gpio3"; function = "qup19"; }; config { pins = "gpio0", "gpio1", "gpio2", "gpio3"; drive-strength = <6>; bias-disable; }; }; qup_uart2_default: qup-uart2-default { mux { pins = "gpio117", "gpio118"; function = "qup2"; }; }; qup_uart6_default: qup-uart6-default { mux { pins = "gpio16", "gpio17", "gpio18", "gpio19"; function = "qup6"; }; }; qup_uart12_default: qup-uart12-default { mux { pins = "gpio34", "gpio35"; function = "qup12"; }; }; qup_uart17_default: qup-uart17-default { mux { pins = "gpio52", "gpio53", "gpio54", "gpio55"; function = "qup17"; }; }; qup_uart18_default: qup-uart18-default { mux { pins = "gpio58", "gpio59"; function = "qup18"; }; }; }; adsp: remoteproc@17300000 { compatible = "qcom,sm8250-adsp-pas"; reg = <0 0x17300000 0 0x100>; interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>, <&rpmhpd SM8250_LCX>, <&rpmhpd SM8250_LMX>; power-domain-names = "load_state", "lcx", "lmx"; memory-region = <&adsp_mem>; qcom,smem-states = <&smp2p_adsp_out 0>; qcom,smem-state-names = "stop"; status = "disabled"; glink-edge { interrupts-extended = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP>; label = "lpass"; qcom,remote-pid = <2>; }; }; intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; interrupt-controller; reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ interrupts = ; }; watchdog@17c10000 { compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt"; reg = <0 0x17c10000 0 0x1000>; clocks = <&sleep_clk>; }; timer@17c20000 { #address-cells = <2>; #size-cells = <2>; ranges; compatible = "arm,armv7-timer-mem"; reg = <0x0 0x17c20000 0x0 0x1000>; clock-frequency = <19200000>; frame@17c21000 { frame-number = <0>; interrupts = , ; reg = <0x0 0x17c21000 0x0 0x1000>, <0x0 0x17c22000 0x0 0x1000>; }; frame@17c23000 { frame-number = <1>; interrupts = ; reg = <0x0 0x17c23000 0x0 0x1000>; status = "disabled"; }; frame@17c25000 { frame-number = <2>; interrupts = ; reg = <0x0 0x17c25000 0x0 0x1000>; status = "disabled"; }; frame@17c27000 { frame-number = <3>; interrupts = ; reg = <0x0 0x17c27000 0x0 0x1000>; status = "disabled"; }; frame@17c29000 { frame-number = <4>; interrupts = ; reg = <0x0 0x17c29000 0x0 0x1000>; status = "disabled"; }; frame@17c2b000 { frame-number = <5>; interrupts = ; reg = <0x0 0x17c2b000 0x0 0x1000>; status = "disabled"; }; frame@17c2d000 { frame-number = <6>; interrupts = ; reg = <0x0 0x17c2d000 0x0 0x1000>; status = "disabled"; }; }; apps_rsc: rsc@18200000 { label = "apps_rsc"; compatible = "qcom,rpmh-rsc"; reg = <0x0 0x18200000 0x0 0x10000>, <0x0 0x18210000 0x0 0x10000>, <0x0 0x18220000 0x0 0x10000>; reg-names = "drv-0", "drv-1", "drv-2"; interrupts = , , ; qcom,tcs-offset = <0xd00>; qcom,drv-id = <2>; qcom,tcs-config = , , , ; rpmhcc: clock-controller { compatible = "qcom,sm8250-rpmh-clk"; #clock-cells = <1>; clock-names = "xo"; clocks = <&xo_board>; }; rpmhpd: power-controller { compatible = "qcom,sm8250-rpmhpd"; #power-domain-cells = <1>; operating-points-v2 = <&rpmhpd_opp_table>; rpmhpd_opp_table: opp-table { compatible = "operating-points-v2"; rpmhpd_opp_ret: opp1 { opp-level = ; }; rpmhpd_opp_min_svs: opp2 { opp-level = ; }; rpmhpd_opp_low_svs: opp3 { opp-level = ; }; rpmhpd_opp_svs: opp4 { opp-level = ; }; rpmhpd_opp_svs_l1: opp5 { opp-level = ; }; rpmhpd_opp_nom: opp6 { opp-level = ; }; rpmhpd_opp_nom_l1: opp7 { opp-level = ; }; rpmhpd_opp_nom_l2: opp8 { opp-level = ; }; rpmhpd_opp_turbo: opp9 { opp-level = ; }; rpmhpd_opp_turbo_l1: opp10 { opp-level = ; }; }; }; apps_bcm_voter: bcm_voter { compatible = "qcom,bcm-voter"; }; }; epss_l3: interconnect@18590000 { compatible = "qcom,sm8250-epss-l3"; reg = <0 0x18590000 0 0x1000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; clock-names = "xo", "alternate"; #interconnect-cells = <1>; }; cpufreq_hw: cpufreq@18591000 { compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss"; reg = <0 0x18591000 0 0x1000>, <0 0x18592000 0 0x1000>, <0 0x18593000 0 0x1000>; reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; clock-names = "xo", "alternate"; #freq-domain-cells = <1>; }; }; timer { compatible = "arm,armv8-timer"; interrupts = , , , ; }; thermal-zones { cpu0-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 1>; trips { cpu0_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu0_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu0_crit: cpu_crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu0_alert0>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu0_alert1>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu1-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 2>; trips { cpu1_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu1_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu1_crit: cpu_crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu1_alert0>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu1_alert1>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu2-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 3>; trips { cpu2_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu2_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu2_crit: cpu_crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu2_alert0>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu2_alert1>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu3-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 4>; trips { cpu3_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu3_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu3_crit: cpu_crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu3_alert0>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu3_alert1>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu4-top-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 7>; trips { cpu4_top_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu4_top_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu4_top_crit: cpu_crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu4_top_alert0>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu4_top_alert1>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu5-top-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 8>; trips { cpu5_top_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu5_top_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu5_top_crit: cpu_crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu5_top_alert0>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu5_top_alert1>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu6-top-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 9>; trips { cpu6_top_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu6_top_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu6_top_crit: cpu_crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu6_top_alert0>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu6_top_alert1>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu7-top-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 10>; trips { cpu7_top_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu7_top_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu7_top_crit: cpu_crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu7_top_alert0>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu7_top_alert1>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu4-bottom-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 11>; trips { cpu4_bottom_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu4_bottom_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu4_bottom_crit: cpu_crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu4_bottom_alert0>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu4_bottom_alert1>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu5-bottom-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 12>; trips { cpu5_bottom_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu5_bottom_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu5_bottom_crit: cpu_crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu5_bottom_alert0>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu5_bottom_alert1>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu6-bottom-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 13>; trips { cpu6_bottom_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu6_bottom_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu6_bottom_crit: cpu_crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu6_bottom_alert0>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu6_bottom_alert1>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu7-bottom-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 14>; trips { cpu7_bottom_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu7_bottom_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu7_bottom_crit: cpu_crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu7_bottom_alert0>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu7_bottom_alert1>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; aoss0-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 0>; trips { aoss0_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; }; }; cluster0-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 5>; trips { cluster0_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; cluster0_crit: cluster0_crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; }; }; }; cluster1-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 6>; trips { cluster1_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; cluster1_crit: cluster1_crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; }; }; }; gpu-thermal-top { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 15>; trips { gpu1_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; }; }; aoss1-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens1 0>; trips { aoss1_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; }; }; wlan-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens1 1>; trips { wlan_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; }; }; video-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens1 2>; trips { video_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; }; }; mem-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens1 3>; trips { mem_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; }; }; q6-hvx-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens1 4>; trips { q6_hvx_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; }; }; camera-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens1 5>; trips { camera_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; }; }; compute-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens1 6>; trips { compute_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; }; }; npu-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens1 7>; trips { npu_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; }; }; gpu-thermal-bottom { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens1 8>; trips { gpu2_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; }; }; }; };