Lines Matching full:operand
89 void AssemblerAarch64::Ldp(const Register &rt, const Register &rt2, const MemoryOperand &operand) in Ldp() argument
92 if (operand.IsImmediateOffset()) { in Ldp()
93 switch (operand.GetAddrMode()) { in Ldp()
108 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value()); in Ldp()
115 Rn(operand.GetRegBase().GetId()) | Rt(rt.GetId()); in Ldp()
123 void AssemblerAarch64::Stp(const Register &rt, const Register &rt2, const MemoryOperand &operand) in Stp() argument
126 if (operand.IsImmediateOffset()) { in Stp()
127 switch (operand.GetAddrMode()) { in Stp()
142 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value()); in Stp()
149 Rn(operand.GetRegBase().GetId()) | Rt(rt.GetId()); in Stp()
157 …blerAarch64::Ldp(const VectorRegister &vt, const VectorRegister &vt2, const MemoryOperand &operand) in Ldp() argument
160 if (operand.IsImmediateOffset()) { in Ldp()
161 switch (operand.GetAddrMode()) { in Ldp()
175 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value()); in Ldp()
195 Rn(operand.GetRegBase().GetId()) | Rt(vt.GetId()); in Ldp()
203 …blerAarch64::Stp(const VectorRegister &vt, const VectorRegister &vt2, const MemoryOperand &operand) in Stp() argument
206 if (operand.IsImmediateOffset()) { in Stp()
207 switch (operand.GetAddrMode()) { in Stp()
221 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value()); in Stp()
241 Rn(operand.GetRegBase().GetId()) | Rt(vt.GetId()); in Stp()
276 void AssemblerAarch64::Ldr(const Register &rt, const MemoryOperand &operand, Scale scale) in Ldr() argument
279 uint32_t op = GetOpcodeOfLdr(operand, scale); in Ldr()
280 if (operand.IsImmediateOffset()) { in Ldr()
281 uint64_t imm = GetImmOfLdr(operand, scale, regX); in Ldr()
282 bool isSigned = operand.GetAddrMode() != AddrMode::OFFSET; in Ldr()
285 Rn(operand.GetRegBase().GetId()) | Rt(rt.GetId()); in Ldr()
288 ASSERT(operand.GetExtendOption() != Extend::NO_EXTEND); in Ldr()
289 uint32_t shift = GetShiftOfLdr(operand, scale, regX); in Ldr()
290 Register rm = operand.GetRegisterOffset(); in Ldr()
291 Register rn = operand.GetRegBase(); in Ldr()
293 (operand.GetExtendOption() << LDR_STR_Extend_LOWBITS) & LDR_STR_Extend_MASK; in Ldr()
302 void AssemblerAarch64::Ldr(const Register &rt, const MemoryOperand &operand) in Ldr() argument
304 Ldr(rt, operand, Scale::Q); in Ldr()
307 void AssemblerAarch64::Ldrh(const Register &rt, const MemoryOperand &operand) in Ldrh() argument
310 Ldr(rt, operand, Scale::H); in Ldrh()
313 void AssemblerAarch64::Ldrb(const Register &rt, const MemoryOperand &operand) in Ldrb() argument
316 Ldr(rt, operand, Scale::B); in Ldrb()
319 void AssemblerAarch64::Str(const Register &rt, const MemoryOperand &operand) in Str() argument
324 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value()); in Str()
325 if (operand.IsImmediateOffset()) { in Str()
326 switch (operand.GetAddrMode()) { in Str()
348 Rn(operand.GetRegBase().GetId()) | Rt(rt.GetId()); in Str()
356 void AssemblerAarch64::Ldur(const Register &rt, const MemoryOperand &operand) in Ldur() argument
360 ASSERT(operand.IsImmediateOffset()); in Ldur()
361 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value()); in Ldur()
364 Rn(operand.GetRegBase().GetId()) | Rt(rt.GetId()); in Ldur()
368 void AssemblerAarch64::Stur(const Register &rt, const MemoryOperand &operand) in Stur() argument
372 ASSERT(operand.IsImmediateOffset()); in Stur()
373 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value()); in Stur()
376 Rn(operand.GetRegBase().GetId()) | Rt(rt.GetId()); in Stur()
461 Add(rd, rm, Operand(Immediate(0))); in Mov()
463 Orr(rd, Register(Zero), Operand(rm)); in Mov()
632 …firstshift = (tz / 16) * 16; // 16 : 16 means the operand of MOVK/N/Z is 16 bits Immediate in EmitMovInstruct()
634 …lastshift = ((63 - lz) / 16) * 16; // 16 : 16 means the operand of MOVK/N/Z is 16 bits Immediate in EmitMovInstruct()
647 … firstshift += 16; // 16 : 16 means the operand of MOVK is 16 bits Immediate in EmitMovInstruct()
696 void AssemblerAarch64::Orr(const Register &rd, const Register &rn, const Operand &operand) in Orr() argument
698 ASSERT(operand.IsShifted()); in Orr()
699 BitWiseOpShift(ORR_Shift, rd, rn, operand); in Orr()
702 void AssemblerAarch64::And(const Register &rd, const Register &rn, const Operand &operand) in And() argument
704 ASSERT(operand.IsShifted()); in And()
705 BitWiseOpShift(AND_Shift, rd, rn, operand); in And()
708 void AssemblerAarch64::Ands(const Register &rd, const Register &rn, const Operand &operand) in Ands() argument
710 ASSERT(operand.IsShifted()); in Ands()
711 BitWiseOpShift(ANDS_Shift, rd, rn, operand); in Ands()
720 …4::BitWiseOpShift(BitwiseOpCode op, const Register &rd, const Register &rn, const Operand &operand) in BitWiseOpShift() argument
722 …uint32_t shift_field = (operand.GetShiftOption() << BITWISE_OP_Shift_LOWBITS) & BITWISE_OP_Shift_M… in BitWiseOpShift()
723 …uint32_t shift_amount = (operand.GetShiftAmount() << BITWISE_OP_ShiftAmount_LOWBITS) & BITWISE_OP_… in BitWiseOpShift()
724 uint32_t code = Sf(!rd.IsW()) | op | shift_field | Rm(operand.Reg().GetId()) | in BitWiseOpShift()
768 void AssemblerAarch64::Add(const Register &rd, const Register &rn, const Operand &operand) in Add() argument
770 if (operand.IsImmediate()) { in Add()
771 int64_t imm = static_cast<int64_t>(operand.ImmediateValue()); in Add()
778 if (operand.IsShifted()) { in Add()
779 AddSubReg(ADD_Shift, rd, rn, false, operand); in Add()
781 AddSubReg(ADD_Extend, rd, rn, false, operand); in Add()
786 void AssemblerAarch64::Adds(const Register &rd, const Register &rn, const Operand &operand) in Adds() argument
788 if (operand.IsImmediate()) { in Adds()
789 AddSubImm(ADD_Imm, rd, rn, true, operand.ImmediateValue()); in Adds()
791 if (operand.IsShifted()) { in Adds()
792 AddSubReg(ADD_Shift, rd, rn, true, operand); in Adds()
794 AddSubReg(ADD_Extend, rd, rn, true, operand); in Adds()
799 void AssemblerAarch64::Sub(const Register &rd, const Register &rn, const Operand &operand) in Sub() argument
801 if (operand.IsImmediate()) { in Sub()
802 int64_t imm = static_cast<int64_t>(operand.ImmediateValue()); in Sub()
809 if (operand.IsShifted()) { in Sub()
810 AddSubReg(SUB_Shift, rd, rn, false, operand); in Sub()
812 AddSubReg(SUB_Extend, rd, rn, false, operand); in Sub()
817 void AssemblerAarch64::Subs(const Register &rd, const Register &rn, const Operand &operand) in Subs() argument
819 if (operand.IsImmediate()) { in Subs()
820 AddSubImm(SUB_Imm, rd, rn, true, operand.ImmediateValue()); in Subs()
822 if (operand.IsShifted()) { in Subs()
823 AddSubReg(SUB_Shift, rd, rn, true, operand); in Subs()
825 AddSubReg(SUB_Extend, rd, rn, true, operand); in Subs()
862 bool setFlags, const Operand &operand) in AddSubReg() argument
866 if (operand.IsShifted()) { in AddSubReg()
867 … uint32_t shift_field = ((operand.GetShiftOption()) << ADD_SUB_Shift_LOWBITS) & ADD_SUB_Shift_MASK; in AddSubReg()
868 …uint32_t shift_amount = ((operand.GetShiftAmount()) << ADD_SUB_ShiftAmount_LOWBITS) & ADD_SUB_Shif… in AddSubReg()
870 code = Sf(!rd.IsW()) | op | flags_field | shift_field | Rm(operand.Reg().GetId()) | in AddSubReg()
875 (operand.GetExtendOption() << ADD_SUB_ExtendOption_LOWBITS) & ADD_SUB_ExtendOption_MASK; in AddSubReg()
876 …uint32_t extend_shift = (operand.GetShiftAmount() << ADD_SUB_ExtendShift_LOWBITS) & ADD_SUB_Extend… in AddSubReg()
877 code = Sf(!rd.IsW()) | op | flags_field | Rm(operand.Reg().GetId()) | extend_field | in AddSubReg()
883 void AssemblerAarch64::Cmp(const Register &rd, const Operand &operand) in Cmp() argument
885 Subs(Register(Zero, rd.GetType()), rd, operand); in Cmp()
888 void AssemblerAarch64::CMov(const Register &rd, const Register &rn, const Operand &operand, Conditi… in CMov() argument
890 ASSERT(!operand.IsImmediate()); in CMov()
892 …uint32_t code = Sf(!rd.IsW()) | CSEL | Rm(operand.Reg().GetId()) | cond_field | Rn(rn.GetId()) | R… in CMov()
1135 uint64_t AssemblerAarch64::GetImmOfLdr(const MemoryOperand &operand, Scale scale, bool isRegX) in GetImmOfLdr() argument
1137 ASSERT(operand.IsImmediateOffset()); in GetImmOfLdr()
1138 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value()); in GetImmOfLdr()
1139 if (operand.GetAddrMode() == OFFSET) { in GetImmOfLdr()
1153 uint64_t AssemblerAarch64::GetOpcodeOfLdr(const MemoryOperand &operand, Scale scale) in GetOpcodeOfLdr() argument
1156 if (operand.IsImmediateOffset()) { in GetOpcodeOfLdr()
1157 switch (operand.GetAddrMode()) { in GetOpcodeOfLdr()
1216 uint32_t AssemblerAarch64::GetShiftOfLdr(const MemoryOperand &operand, Scale scale, bool isRegX) in GetShiftOfLdr() argument
1220 shift = operand.GetShiftOption() != Shift::NO_SHIFT; in GetShiftOfLdr()
1222 shift = operand.GetShiftAmount(); in GetShiftOfLdr()
1226 shift = operand.GetShiftAmount(); in GetShiftOfLdr()