Lines Matching +full:protected +full:- +full:clocks
1 This binding is a work-in-progress, and are based on some experimental
10 value of a #clock-cells property in the clock provider node.
17 #clock-cells: Number of cells in a clock specifier; Typically 0 for nodes
22 clock-output-names: Recommended to be a list of strings of clock output signal
24 However, the meaning of clock-output-names is domain
33 the provider's clock-output-names property.
38 #clock-cells = <1>;
39 clock-output-names = "ckil", "ckih";
42 - this node defines a device with two clock outputs, the first named
44 clocks by index. The names should reflect the clock output signal
47 clock-indices: If the identifying number for the clocks in the node
49 identifiers into the clock-output-names array.
51 For example, if we have two clocks <&oscillator 1> and <&oscillator 3>:
55 #clock-cells = <1>;
56 clock-indices = <1>, <3>;
57 clock-output-names = "clka", "clkb";
60 This ensures we do not have any empty strings in clock-output-names
66 clocks: List of phandle and clock specifier pairs, one pair
68 clock provider specifies '0' for #clock-cells, then
72 clock-names: List of clock input name strings sorted in the same
73 order as the clocks property. Consumers drivers
74 will use clock-names to match clock input names
75 with clocks specifiers.
76 clock-ranges: Empty property indicating that child nodes can inherit named
77 clocks from this node. Useful for bus nodes to provide a
83 clocks = <&osc 1>, <&ref 0>;
84 clock-names = "baud", "register";
96 compatible = "fixed-clock";
97 #clock-cells = <0>;
98 clock-frequency = <32678>;
99 clock-output-names = "osc";
102 /* phase-locked-loop device, generates a higher frequency clock
105 compatible = "vendor,some-pll-interface"
106 #clock-cells = <1>;
107 clocks = <&osc 0>;
108 clock-names = "ref";
110 clock-output-names = "pll", "pll-switched";
117 compatible = "fsl,imx-uart";
120 clocks = <&osc 0>, <&pll 1>;
121 clock-names = "baud", "register";
125 low-frequency reference clock, a PLL device to generate a higher frequency
128 * The oscillator is fixed-frequency, and provides one clock output, named "osc".
131 ("pll" and "pll-switched").
133 register clock connected to the PLL clock (the "pll-switched" signal)
137 Some platforms may require initial configuration of default parent clocks
139 node through assigned-clocks, assigned-clock-parents and assigned-clock-rates
140 properties. The assigned-clock-parents property should contain a list of parent
141 clocks in the form of a phandle and clock specifier pair and the
142 assigned-clock-rates property should contain a list of frequencies in Hz. Both
143 these properties should correspond to the clocks listed in the assigned-clocks
147 set to 0, or can be omitted if it is not followed by any non-zero entry.
150 compatible = "fsl,imx-uart";
153 clocks = <&osc 0>, <&pll 1>;
154 clock-names = "baud", "register";
156 assigned-clocks = <&clkcon 0>, <&pll 2>;
157 assigned-clock-parents = <&pll 2>;
158 assigned-clock-rates = <0>, <460800>;
165 the clock can be done only for clocks that have a single user. Specifying
169 Configuration of common clocks, which affect multiple consumer devices can
172 ==Protected clocks==
174 Some platforms or firmwares may not fully expose all the clocks to the OS, such
177 protected-clocks property in the form of a clock specifier list. This property should
178 only be specified in the node that is providing the clocks being protected:
180 clock-controller@a000f000 {
183 #clocks-cells = <1>;
185 protected-clocks = <UART3_CLK>, <SPI5_CLK>;