Lines Matching refs:should

29 - reg: should be register base and length as documented in the
40   Ports 0 and 1 should correspond to CSI0 and CSI1,
41   ports 2 and 3 should correspond to DI0 and DI1, respectively.
66 - compatible: should be "fsl,imx6qp-pre"
67 - reg: should be register base and length as documented in the
72 - clock-names: should be "axi"
73 - interrupts: should contain the PRE interrupt
74 - fsl,iram: phandle pointing to the mmio-sram device node, that should be
92 - compatible: should be "fsl,imx6qp-prg"
93 - reg: should be register base and length as documented in the
98 - clock-names: should be "ipg" and "axi"