Lines Matching +full:0 +full:x900
19 configuration registers. For mt8173 this must be offset 0x900 into the
20 MMSYS_CONFIG region: <&mmsys 0x900>.
23 - port@0: The input port in the ports node should be connected to a DPI output
67 - #phy-cells: must be <0>
68 - #clock-cells: must be <0>
71 - mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa
72 - mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c
78 reg = <0 0x10013000 0 0xbc>;
85 reg = <0 0x10209100 0 0x24>;
89 mediatek,ibias = <0xa>;
90 mediatek,ibias_up = <0x1c>;
91 #clock-cells = <0>;
92 #phy-cells = <0>;
97 reg = <0 0x11012000 0 0x1c>;
105 reg = <0 0x14025000 0 0x400>;
113 pinctrl-0 = <&hdmi_pin>;
116 mediatek,syscon-hdmi = <&mmsys 0x900>;
122 #size-cells = <0>;
124 port@0 {
125 reg = <0>;