Lines Matching +full:dma +full:- +full:channels
1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dma-spear1340.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys Designware DMA Controller
10 - Viresh Kumar <vireshk@kernel.org>
11 - Andy Shevchenko <andriy.shevchenko@linux.intel.com>
14 - $ref: "dma-controller.yaml#"
18 const: snps,dma-spear1340
20 "#dma-cells":
24 First cell is a phandle pointing to the DMA controller. Second one is
25 the DMA request line number. Third cell is the memory master identifier
28 cell is an optional mask of the DMA channels permitted to be allocated
40 clock-names:
44 dma-channels:
46 Number of DMA channels supported by the controller. In case if
47 not specified the driver will try to auto-detect this and
52 dma-requests:
56 dma-masters:
59 Number of DMA masters supported by the controller. In case if
60 not specified the driver will try to auto-detect this and
68 DMA channels allocation order specifier. Zero means ascending order
69 (first free allocated), while one - descending (last free allocated).
76 DMA channels priority order. Zero means ascending channels priority
84 description: Maximum block size supported by the DMA controller.
87 data-width:
88 $ref: /schemas/types.yaml#/definitions/uint32-array
89 description: Data bus width per each DMA master in bytes.
96 $ref: /schemas/types.yaml#/definitions/uint32-array
99 Data bus width per each DMA master in (2^n * 8) bits. This property is
100 deprecated. It' usage is discouraged in favor of data-width one. Moreover
101 the property incorrectly permits to define data-bus width of 8 and 16
102 bits, which is impossible in accordance with DW DMAC IP-core data book.
107 - 0 # 8 bits
108 - 1 # 16 bits
109 - 2 # 32 bits
110 - 3 # 64 bits
111 - 4 # 128 bits
112 - 5 # 256 bits
115 multi-block:
116 $ref: /schemas/types.yaml#/definitions/uint32-array
118 LLP-based multi-block transfer supported by hardware per
119 each DMA channel.
126 snps,max-burst-len:
127 $ref: /schemas/types.yaml#/definitions/uint32-array
130 This property defines the upper limit of the run-time burst setting
132 will be from 1 to max-burst-len words. It's an array property with one
141 snps,dma-protection-control:
144 Bits one-to-one passed to the AHB HPROT[3:1] bus. Each bit setting
145 indicates the following features: bit 0 - privileged mode,
146 bit 1 - DMA is bufferable, bit 2 - DMA is cacheable.
154 - compatible
155 - "#dma-cells"
156 - reg
157 - interrupts
160 - |
161 dma-controller@fc000000 {
162 compatible = "snps,dma-spear1340";
164 interrupt-parent = <&vic1>;
167 dma-channels = <8>;
168 dma-requests = <16>;
169 dma-masters = <4>;
170 #dma-cells = <3>;
175 data-width = <8 8>;
176 multi-block = <0 0 0 0 0 0 0 0>;
177 snps,max-burst-len = <16 16 4 4 4 4 4 4>;