Lines Matching +full:device +full:- +full:tree
1 FPGA Region Device Tree Binding
6 - Introduction
7 - Terminology
8 - Sequence
9 - FPGA Region
10 - Supported Use Models
11 - Device Tree Examples
12 - Constraints
19 the Device Tree. FPGA Regions provide a way to program FPGAs under device tree
22 This device tree binding document hits some of the high points of FPGA usage and
68 device tree.
82 ---------------- ----------------------------------
85 | ----| | ----------- -------- |
87 | | W | | | ----------- -------- |
89 | | B |<=====>|<==| ----------- -------- |
91 | | I | | | ----------- -------- |
93 | | G | | | ----------- -------- |
95 | ----| | ----------- -------- |
97 ---------------- ----------------------------------
100 region (PRR0-2) gets its own split of the busses that is independently gated by
101 a soft logic bridge (Bridge0-2) in the FPGA. The contents of each PRR can be
114 4. The Device Tree overlay is accepted into the live tree.
124 FPGA Regions represent FPGA's and FPGA PR regions in the device tree. An FPGA
130 * image-specific information needed to to the programming.
133 The intended use is that a Device Tree overlay (DTO) can be used to reprogram an
136 An FPGA Region that exists in the live Device Tree reflects the current state.
137 If the live tree shows a "firmware-name" property or child nodes under a FPGA
139 and adds the "firmware-name" property is taken as a request to reprogram the
141 tree.
143 The base FPGA Region in the device tree represents the FPGA and supports full
167 - compatible : should contain "fpga-region"
168 - fpga-mgr : should contain a phandle to an FPGA Manager. Child FPGA Regions
169 inherit this property from their ancestor regions. A fpga-mgr property
171 - #address-cells, #size-cells, ranges : must be present to handle address space
175 - firmware-name : should contain the name of an FPGA image file located on the
176 firmware search path. If this property shows up in a live device tree
180 - fpga-bridges : should contain a list of phandles to FPGA Bridges that must be
183 If the fpga-region is the child of a fpga-bridge, the list should not
185 - partial-fpga-config : boolean, set if partial reconfiguration is to be done,
187 - external-fpga-config : boolean, set if the FPGA has already been configured
189 - encrypted-fpga-config : boolean, set if the bitstream is encrypted
190 - region-unfreeze-timeout-us : The maximum time in microseconds to wait for
193 - region-freeze-timeout-us : The maximum time in microseconds to wait for
196 - config-complete-timeout-us : The maximum time in microseconds time for the
198 - child nodes : devices in the FPGA after programming.
200 In the example below, when an overlay is applied targeting fpga-region0,
204 fpga-bridges property. During programming, these bridges are disabled, the
207 reenabled and the overlay makes it into the live device tree. The child devices
214 Base tree contains:
216 fpga_mgr: fpga-mgr@ff706000 {
217 compatible = "altr,socfpga-fpga-mgr";
223 fpga_bridge0: fpga-bridge@ff400000 {
224 compatible = "altr,socfpga-lwhps2fpga-bridge";
229 #address-cells = <1>;
230 #size-cells = <1>;
233 fpga_region0: fpga-region0 {
234 compatible = "fpga-region";
235 fpga-mgr = <&fpga_mgr>;
239 fpga_bridge1: fpga-bridge@ff500000 {
240 compatible = "altr,socfpga-hps2fpga-bridge";
248 /dts-v1/ /plugin/;
252 #address-cells = <1>;
253 #size-cells = <1>;
255 #address-cells = <1>;
256 #size-cells = <1>;
258 firmware-name = "soc_system.rbf";
259 fpga-bridges = <&fpga_bridge1>;
264 compatible = "altr,pio-1.0";
267 #gpio-cells = <2>;
269 gpio-controller;
272 onchip-memory {
274 compatible = "altr,onchipmem-15.1";
286 a FPGA Region. The target of the Device Tree Overlay is the FPGA Region. Some
287 uses are specific to a FPGA device.
300 fpga-bridges property in the FPGA region or in the device tree overlay.
308 PRR's with FPGA bridges. The device tree should have a FPGA region for each
311 Device Tree Examples
320 * target-path or target
322 For the purposes of this section, I'm dividing the Device Tree into two parts,
327 The live Device Tree must contain an FPGA Region, an FPGA Manager, and any FPGA
328 Bridges. The FPGA Region's "fpga-mgr" property specifies the manager by phandle
331 they are specified in the FPGA Region by the "fpga-bridges" property. During
333 "fpga-bridges" list and will re-enable them after FPGA programming has
336 The Device Tree Overlay will contain:
337 * "target-path" or "target"
339 live tree. target-path is a full path, while target is a phandle.
342 * "firmware-name"
345 * "partial-fpga-config"
351 Device Tree Example: Full Reconfiguration without Bridges
354 Live Device Tree contains:
355 fpga_mgr0: fpga-mgr@f8007000 {
356 compatible = "xlnx,zynq-devcfg-1.0";
358 interrupt-parent = <&intc>;
361 clock-names = "ref_clk";
365 fpga_region0: fpga-region0 {
366 compatible = "fpga-region";
367 fpga-mgr = <&fpga_mgr0>;
368 #address-cells = <0x1>;
369 #size-cells = <0x1>;
374 /dts-v1/ /plugin/;
378 #address-cells = <1>;
379 #size-cells = <1>;
381 #address-cells = <1>;
382 #size-cells = <1>;
384 firmware-name = "zynq-gpio.bin";
387 compatible = "xlnx,xps-gpio-1.00.a";
389 gpio-controller;
390 #gpio-cells = <0x2>;
391 xlnx,gpio-width= <0x6>;
396 Device Tree Example: Full Reconfiguration to add PRR's
405 /dts-v1/ /plugin/;
409 #address-cells = <1>;
410 #size-cells = <1>;
412 #address-cells = <1>;
413 #size-cells = <1>;
415 firmware-name = "base.rbf";
417 fpga-bridge@4400 {
418 compatible = "altr,freeze-bridge-controller";
421 fpga_region1: fpga-region1 {
422 compatible = "fpga-region";
423 #address-cells = <0x1>;
424 #size-cells = <0x1>;
429 fpga-bridge@4420 {
430 compatible = "altr,freeze-bridge-controller";
433 fpga_region2: fpga-region2 {
434 compatible = "fpga-region";
435 #address-cells = <0x1>;
436 #size-cells = <0x1>;
444 Device Tree Example: Partial Reconfiguration
451 "partial-fpga-config" boolean and the only bridge that is controlled during
454 /dts-v1/ /plugin/;
458 #address-cells = <1>;
459 #size-cells = <1>;
461 #address-cells = <1>;
462 #size-cells = <1>;
464 firmware-name = "soc_image2.rbf";
465 partial-fpga-config;
468 compatible = "altr,pio-1.0";
472 #gpio-cells = <0x2>;
473 gpio-controller;
493 --
494 [1] www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_partrecon.pdf