Lines Matching full:plic

5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
12   (PLIC) high-level specification in the RISC-V Privileged Architecture
13   specification. The PLIC connects all external interrupts in the system to all
25   with priority below this threshold will not cause the PLIC to raise its
28   While the PLIC supports both edge-triggered and level-triggered interrupts,
30   specified in the PLIC device-tree binding.
32   While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
33   "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
45       - const: sifive,fu540-c000-plic
46       - const: sifive,plic-1.0.0
62       Specifies which contexts are connected to the PLIC, with "-1" specifying
84     plic: interrupt-controller@c000000 {
87       compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";