Lines Matching +full:imx8qxp +full:- +full:mu

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/fsl,mu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX Messaging Unit (MU)
10   - Dong Aisheng <aisheng.dong@nxp.com>
15   and control) through the MU interface. The MU also provides the ability
18   Because the MU manages the messaging between processors, the MU uses
20   Therefore, the MU must synchronize the accesses from one side to the
21   other. The MU accomplishes synchronization using two sets of matching
22   registers (Processor A-facing, Processor B-facing).
27       - const: fsl,imx6sx-mu
28       - const: fsl,imx7ulp-mu
29       - const: fsl,imx8-mu-scu
30       - items:
31           - enum:
32               - fsl,imx7s-mu
33               - fsl,imx8mq-mu
34               - fsl,imx8mm-mu
35               - fsl,imx8mn-mu
36               - fsl,imx8mp-mu
37               - fsl,imx8qxp-mu
38           - const: fsl,imx6sx-mu
39       - description: To communicate with i.MX8 SCU with fast IPC
41           - const: fsl,imx8-mu-scu
42           - const: fsl,imx8qxp-mu
43           - const: fsl,imx6sx-mu
51   "#mbox-cells":
58       This MU support 4 type of unidirectional channels, each type
61       0 - TX channel with 32bit transmit register and IRQ transmit
63       1 - RX channel with 32bit receive register and IRQ support
64       2 - TX doorbell channel. Without own register and no ACK support.
65       3 - RX doorbell channel.
71   fsl,mu-side-b:
72     description: boolean, if present, means it is for side B MU.
75   power-domains:
79   - compatible
80   - reg
81   - interrupts
82   - "#mbox-cells"
87   - |
88     #include <dt-bindings/interrupt-controller/arm-gic.h>
91         compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
94         #mbox-cells = <2>;