Lines Matching +full:interrupt +full:- +full:map
4 - compatible: Should contain one of the following strings:
5 "mediatek,mt2701-pcie"
6 "mediatek,mt2712-pcie"
7 "mediatek,mt7622-pcie"
8 "mediatek,mt7623-pcie"
9 "mediatek,mt7629-pcie"
10 - device_type: Must be "pci"
11 - reg: Base addresses and lengths of the PCIe subsys and root ports.
12 - reg-names: Names of the above areas to use during resource lookup.
13 - #address-cells: Address representation for root ports (must be 3)
14 - #size-cells: Size representation for root ports (must be 2)
15 - clocks: Must contain an entry for each entry in clock-names.
16 See ../clocks/clock-bindings.txt for details.
17 - clock-names:
19 - sys_ckN :transaction layer and data link layer clock
21 - free_ck :for reference clock of PCIe subsys
23 - ahb_ckN :AHB slave interface operating clock for CSR access and RC
26 - axi_ckN :application layer MMIO channel operating clock
27 - aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when
29 - obff_ckN :OBFF functional block operating clock
30 - pipe_ckN :LTSSM and PHY/MAC layer operating clock
32 - phys: List of PHY specifiers (used by generic PHY framework).
33 - phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
35 - power-domains: A phandle and power domain specifier pair to the power domain
37 - bus-range: Range of bus numbers associated with this controller.
38 - ranges: Ranges for the PCI memory and I/O regions.
41 - #interrupt-cells: Size representation for interrupts (must be 1)
42 - interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
45 - resets: Must contain an entry for each entry in reset-names.
47 - reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the
51 -interrupts: A list of interrupt outputs of the controller, must have one
54 In addition, the device tree node must have sub-nodes describing each
58 - device_type: Must be "pci"
59 - reg: Only the first four bytes are used to refer to the correct bus number
61 - #address-cells: Must be 3
62 - #size-cells: Must be 2
63 - #interrupt-cells: Must be 1
64 - interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
67 - ranges: Sub-ranges distributed from the PCIe controller node. An empty
73 compatible = "mediatek,mt7623-hifsys",
74 "mediatek,mt2701-hifsys",
77 #clock-cells = <1>;
78 #reset-cells = <1>;
82 compatible = "mediatek,mt7623-pcie";
88 reg-names = "subsys", "port0", "port1", "port2";
89 #address-cells = <3>;
90 #size-cells = <2>;
91 #interrupt-cells = <1>;
92 interrupt-map-mask = <0xf800 0 0 0>;
93 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
100 clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
104 reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
107 phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
108 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
109 bus-range = <0x00 0xff>;
115 #address-cells = <3>;
116 #size-cells = <2>;
117 #interrupt-cells = <1>;
118 interrupt-map-mask = <0 0 0 0>;
119 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
125 #address-cells = <3>;
126 #size-cells = <2>;
127 #interrupt-cells = <1>;
128 interrupt-map-mask = <0 0 0 0>;
129 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
135 #address-cells = <3>;
136 #size-cells = <2>;
137 #interrupt-cells = <1>;
138 interrupt-map-mask = <0 0 0 0>;
139 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
147 compatible = "mediatek,mt2712-pcie";
151 reg-names = "port0", "port1";
152 #address-cells = <3>;
153 #size-cells = <2>;
160 clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
162 phy-names = "pcie-phy0", "pcie-phy1";
163 bus-range = <0x00 0xff>;
168 #address-cells = <3>;
169 #size-cells = <2>;
170 #interrupt-cells = <1>;
172 interrupt-map-mask = <0 0 0 7>;
173 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
177 pcie_intc0: interrupt-controller {
178 interrupt-controller;
179 #address-cells = <0>;
180 #interrupt-cells = <1>;
186 #address-cells = <3>;
187 #size-cells = <2>;
188 #interrupt-cells = <1>;
190 interrupt-map-mask = <0 0 0 7>;
191 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
195 pcie_intc1: interrupt-controller {
196 interrupt-controller;
197 #address-cells = <0>;
198 #interrupt-cells = <1>;
206 compatible = "mediatek,mt7622-pcie";
211 reg-names = "subsys", "port0", "port1";
212 #address-cells = <3>;
213 #size-cells = <2>;
228 clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
232 phy-names = "pcie-phy0", "pcie-phy1";
233 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
234 bus-range = <0x00 0xff>;
239 #address-cells = <3>;
240 #size-cells = <2>;
241 #interrupt-cells = <1>;
243 interrupt-map-mask = <0 0 0 7>;
244 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
248 pcie_intc0: interrupt-controller {
249 interrupt-controller;
250 #address-cells = <0>;
251 #interrupt-cells = <1>;
257 #address-cells = <3>;
258 #size-cells = <2>;
259 #interrupt-cells = <1>;
261 interrupt-map-mask = <0 0 0 7>;
262 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
266 pcie_intc1: interrupt-controller {
267 interrupt-controller;
268 #address-cells = <0>;
269 #interrupt-cells = <1>;