Lines Matching +full:gcc +full:- +full:sm8250
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Manu Gautam <mgautam@codeaurora.org>
20 - qcom,ipq8074-qmp-pcie-phy
21 - qcom,ipq8074-qmp-usb3-phy
22 - qcom,msm8996-qmp-pcie-phy
23 - qcom,msm8996-qmp-ufs-phy
24 - qcom,msm8996-qmp-usb3-phy
25 - qcom,msm8998-qmp-pcie-phy
26 - qcom,msm8998-qmp-ufs-phy
27 - qcom,msm8998-qmp-usb3-phy
28 - qcom,sdm845-qhp-pcie-phy
29 - qcom,sdm845-qmp-pcie-phy
30 - qcom,sdm845-qmp-ufs-phy
31 - qcom,sdm845-qmp-usb3-uni-phy
32 - qcom,sm8150-qmp-ufs-phy
33 - qcom,sm8250-qmp-ufs-phy
37 - description: Address and length of PHY's common serdes block.
39 "#clock-cells":
42 "#address-cells":
45 "#size-cells":
54 clock-names:
62 reset-names:
66 vdda-phy-supply:
70 vdda-pll-supply:
74 vddp-ref-clk-supply:
80 "^phy@[0-9a-f]+$":
87 - compatible
88 - reg
89 - "#clock-cells"
90 - "#address-cells"
91 - "#size-cells"
92 - ranges
93 - clocks
94 - clock-names
95 - resets
96 - reset-names
97 - vdda-phy-supply
98 - vdda-pll-supply
103 - if:
108 - qcom,sdm845-qmp-usb3-uni-phy
113 - description: Phy aux clock.
114 - description: Phy config clock.
115 - description: 19.2 MHz ref clk.
116 - description: Phy common block aux clock.
117 clock-names:
119 - const: aux
120 - const: cfg_ahb
121 - const: ref
122 - const: com_aux
125 - description: reset of phy block.
126 - description: phy common block reset.
127 reset-names:
129 - const: phy
130 - const: common
131 - if:
136 - qcom,msm8996-qmp-pcie-phy
141 - description: Phy aux clock.
142 - description: Phy config clock.
143 - description: 19.2 MHz ref clk.
144 clock-names:
146 - const: aux
147 - const: cfg_ahb
148 - const: ref
151 - description: reset of phy block.
152 - description: phy common block reset.
153 - description: phy's ahb cfg block reset.
154 reset-names:
156 - const: phy
157 - const: common
158 - const: cfg
159 - if:
164 - qcom,ipq8074-qmp-usb3-phy
165 - qcom,msm8996-qmp-usb3-phy
166 - qcom,msm8998-qmp-pcie-phy
167 - qcom,msm8998-qmp-usb3-phy
172 - description: Phy aux clock.
173 - description: Phy config clock.
174 - description: 19.2 MHz ref clk.
175 clock-names:
177 - const: aux
178 - const: cfg_ahb
179 - const: ref
182 - description: reset of phy block.
183 - description: phy common block reset.
184 reset-names:
186 - const: phy
187 - const: common
188 - if:
193 - qcom,msm8996-qmp-ufs-phy
198 - description: 19.2 MHz ref clk.
199 clock-names:
201 - const: ref
204 - description: PHY reset in the UFS controller.
205 reset-names:
207 - const: ufsphy
208 - if:
213 - qcom,msm8998-qmp-ufs-phy
214 - qcom,sdm845-qmp-ufs-phy
215 - qcom,sm8150-qmp-ufs-phy
216 - qcom,sm8250-qmp-ufs-phy
221 - description: 19.2 MHz ref clk.
222 - description: Phy reference aux clock.
223 clock-names:
225 - const: ref
226 - const: ref_aux
229 - description: PHY reset in the UFS controller.
230 reset-names:
232 - const: ufsphy
233 - if:
238 - qcom,ipq8074-qmp-pcie-phy
243 - description: pipe clk.
244 clock-names:
246 - const: pipe_clk
249 - description: reset of phy block.
250 - description: phy common block reset.
251 reset-names:
253 - const: phy
254 - const: common
255 - if:
260 - qcom,sdm845-qhp-pcie-phy
261 - qcom,sdm845-qmp-pcie-phy
266 - description: Phy aux clock.
267 - description: Phy config clock.
268 - description: 19.2 MHz ref clk.
269 - description: Phy refgen clk.
270 clock-names:
272 - const: aux
273 - const: cfg_ahb
274 - const: ref
275 - const: refgen
278 - description: reset of phy block.
279 reset-names:
281 - const: phy
284 - |
285 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
286 usb_2_qmpphy: phy-wrapper@88eb000 {
287 compatible = "qcom,sdm845-qmp-usb3-uni-phy";
289 #clock-cells = <1>;
290 #address-cells = <1>;
291 #size-cells = <1>;
294 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK >,
295 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
296 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
297 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
298 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
300 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
301 <&gcc GCC_USB3_PHY_SEC_BCR>;
302 reset-names = "phy", "common";
304 vdda-phy-supply = <&vdda_usb2_ss_1p2>;
305 vdda-pll-supply = <&vdda_usb2_ss_core>;
312 #clock-cells = <0>;
313 #phy-cells = <0>;
314 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
315 clock-names = "pipe0";
316 clock-output-names = "usb3_uni_phy_pipe_clk_src";