Lines Matching +full:output +full:- +full:low
1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Texas Instruments TLV320ADCX140 Quad Channel Analog-to-Digital Converter
11 - Dan Murphy <dmurphy@ti.com>
14 The TLV320ADCX140 are multichannel (4-ch analog recording or 8-ch digital
15 PDM microphones recording), high-performance audio, analog-to-digital
28 - const: ti,tlv320adc3140
29 - const: ti,tlv320adc5140
30 - const: ti,tlv320adc6140
37 reset-gpios:
41 areg-supply:
46 ti,mic-bias-source:
49 0 - Mic bias is set to VREF
50 1 - Mic bias is set to VREF × 1.096
51 6 - Mic bias is set to AVDD
55 ti,vref-source:
58 0 - Set VREF to 2.75V
59 1 - Set VREF to 2.5V
60 2 - Set VREF to 1.375V
64 ti,pdm-edge-select:
69 0 - (default) Odd channel is latched on the negative edge and even
71 1 - Odd channel is latched on the positive edge and even channel is
74 PDMIN1 - PDMCLK latching edge used for channel 1 and 2 data
75 PDMIN2 - PDMCLK latching edge used for channel 3 and 4 data
76 PDMIN3 - PDMCLK latching edge used for channel 5 and 6 data
77 PDMIN4 - PDMCLK latching edge used for channel 7 and 8 data
79 $ref: /schemas/types.yaml#/definitions/uint32-array
86 ti,gpi-config:
91 0 - (default) disabled
92 1 - GPIX is configured as a general-purpose input (GPI)
93 2 - GPIX is configured as a master clock input (MCLK)
94 3 - GPIX is configured as an ASI input for daisy-chain (SDIN)
95 4 - GPIX is configured as a PDM data input for channel 1 and channel
97 5 - GPIX is configured as a PDM data input for channel 3 and channel
99 6 - GPIX is configured as a PDM data input for channel 5 and channel
101 7 - GPIX is configured as a PDM data input for channel 7 and channel
104 $ref: /schemas/types.yaml#/definitions/uint32-array
111 ti,asi-tx-drive:
114 When set the device will set the Tx ASI output to a Hi-Z state for unused
115 data cycles. Default is to drive the output low on unused ASI cycles.
118 '^ti,gpo-config-[1-4]$':
119 $ref: /schemas/types.yaml#/definitions/uint32-array
121 Defines the configuration and output driver for the general purpose
122 output pins (GPO). These values are pairs, the first value is for the
123 configuration type and the second value is for the output drive type.
126 GPO output configuration can be one of the following:
128 0 - (default) disabled
129 1 - GPOX is configured as a general-purpose output (GPO)
130 2 - GPOX is configured as a device interrupt output (IRQ)
131 3 - GPOX is configured as a secondary ASI output (SDOUT2)
132 4 - GPOX is configured as a PDM clock output (PDMCLK)
134 GPO output drive configuration for the GPO pins can be one of the following:
136 0d - (default) Hi-Z output
137 1d - Drive active low and active high
138 2d - Drive active low and weak high
139 3d - Drive active low and Hi-Z
140 4d - Drive weak low and active high
141 5d - Drive Hi-Z and active high
143 ti,gpio-config:
145 Defines the configuration and output drive for the General Purpose
146 Input and Output pin (GPIO1). Its value is a pair, the first value is for
147 the configuration type and the second value is for the output drive
151 0 - disabled
152 1 - GPIO1 is configured as a general-purpose output (GPO)
153 2 - (default) GPIO1 is configured as a device interrupt output (IRQ)
154 3 - GPIO1 is configured as a secondary ASI output (SDOUT2)
155 4 - GPIO1 is configured as a PDM clock output (PDMCLK)
156 8 - GPIO1 is configured as an input to control when MICBIAS turns on or
158 9 - GPIO1 is configured as a general-purpose input (GPI)
159 10 - GPIO1 is configured as a master clock input (MCLK)
160 11 - GPIO1 is configured as an ASI input for daisy-chain (SDIN)
161 12 - GPIO1 is configured as a PDM data input for channel 1 and channel 2
163 13 - GPIO1 is configured as a PDM data input for channel 3 and channel 4
165 14 - GPIO1 is configured as a PDM data input for channel 5 and channel 6
167 15 - GPIO1 is configured as a PDM data input for channel 7 and channel 8
170 output drive type for the GPIO pin can be one of the following:
171 0 - Hi-Z output
172 1 - Drive active low and active high
173 2 - (default) Drive active low and weak high
174 3 - Drive active low and Hi-Z
175 4 - Drive weak low and active high
176 5 - Drive Hi-Z and active high
179 - $ref: /schemas/types.yaml#/definitions/uint32-array
180 - minItems: 2
187 - compatible
188 - reg
193 - |
194 #include <dt-bindings/gpio/gpio.h>
196 #address-cells = <1>;
197 #size-cells = <0>;
201 ti,mic-bias-source = <6>;
202 ti,pdm-edge-select = <0 1 0 1>;
203 ti,gpi-config = <4 5 6 7>;
204 ti,gpio-config = <10 2>;
205 ti,gpo-config-1 = <0 0>;
206 ti,gpo-config-2 = <0 0>;
207 reset-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;