Lines Matching +full:24 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0 */
14 * __divqu: 64-bit unsigned long divide
15 * __remqu: 64-bit unsigned long remainder
16 * __divqs/__remqs: signed 64-bit
17 * __divlu/__remlu: unsigned 32-bit
18 * __divls/__remls: signed 32-bit
22 * $24 and $25, and return the result in $27. Register $28 may
27 * This is a rather simple bit-at-a-time algorithm: it's very good
28 * at dividing random 64-bit numbers, but the more usual case where
37 * $0 - current bit
38 * $1 - shifted divisor
39 * $2 - modulus/quotient
41 * $23 - return address
42 * $24 - dividend
43 * $25 - divisor
45 * $27 - quotient/modulus
46 * $28 - compare status
67 #define GETSIGN(x) xor $24,$25,x
75 #define GETSIGN(x) bis $24,$24,x
80 * For 32-bit operations, we need to extend to 64-bit
106 bis $24,$24,modulus
110 stq tmp1,24($30)
118 * shift divisor left, using 3-bit shifts for
119 * 32-bit divides as we can't overflow. Three-bit
151 ldq tmp1,24($30)
162 * -a / b = a / -b = -(a / b)
163 * -a % b = -(a % b)
164 * a % -b = a % b
175 bis $24,$25,$28
178 stq $24,0($30)
179 subq $31,$24,$28
181 cmovlt $24,$28,$24 /* abs($24) */
184 stq tmp1,24($30)
188 ldq $24,0($30)
195 ldq tmp1,24($30)