Lines Matching +full:24 +full:- +full:bit

1 /* SPDX-License-Identifier: GPL-2.0 */
3  * arch/alpha/lib/ev6-divide.S
5  * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
14  *	__divqu: 64-bit unsigned long divide
15  *	__remqu: 64-bit unsigned long remainder
16  *	__divqs/__remqs: signed 64-bit
17  *	__divlu/__remlu: unsigned 32-bit
18  *	__divls/__remls: signed 32-bit
22  * $24 and $25, and return the result in $27. Register $28 may
27  * This is a rather simple bit-at-a-time algorithm: it's very good
28  * at dividing random 64-bit numbers, but the more usual case where
37  *	$0 - current bit
38  *	$1 - shifted divisor
39  *	$2 - modulus/quotient
41  *	$23 - return address
42  *	$24 - dividend
43  *	$25 - divisor
45  *	$27 - quotient/modulus
46  *	$28 - compare status
51  *	ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
53  *	E	- either cluster
54  *	U	- upper subcluster; U0 - subcluster U0; U1 - subcluster U1
55  *	L	- lower subcluster; L0 - subcluster L0; L1 - subcluster L1
77 #define GETSIGN(x) xor $24,$25,x
85 #define GETSIGN(x) bis $24,$24,x
90  * For 32-bit operations, we need to extend to 64-bit
117 	bis	$24,$24,modulus		# E :
122 	stq	tmp1,24($30)		# L :
129 	 * In spite of the DIV_ONLY being either a non-instruction
137 	 * shift divisor left, using 3-bit shifts for
138 	 * 32-bit divides as we can't overflow. Three-bit
198 	ldq	tmp1,24($30)		# L :
216  * 	-a / b = a / -b = -(a / b)
217  *	-a % b = -(a % b)
218  *	a % -b = a % b
229 	bis	$24,$25,$28		# E :
233 	stq	$24,0($30)		# L :
234 	subq	$31,$24,$28		# E :
238 	cmovlt	$24,$28,$24	/* abs($24) */ # E : Latency 2, extra map slot
243 	stq	tmp1,24($30)		# L :
248 	ldq	$24,0($30)		# L :
258 	ldq	tmp1,24($30)		# L :