Lines Matching +full:0 +full:xf04
45 * The PB11MPCore has 512 MiB memory @ 0x70000000
46 * and the first 256 are also remapped @ 0x00000000
48 reg = <0x70000000 0x20000000>;
53 #size-cells = <0>;
56 MP11_0: cpu@0 {
59 reg = <0>;
91 reg = <0x1f001000 0x1000>,
92 <0x1f000100 0x100>;
97 reg = <0x1f002000 0x1000>;
99 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>,
100 <0 30 IRQ_TYPE_LEVEL_HIGH>,
101 <0 31 IRQ_TYPE_LEVEL_HIGH>;
121 reg = <0x1f000000 0x100>;
126 reg = <0x1f000600 0x20>;
128 interrupts = <1 13 0xf04>;
133 reg = <0x1f000620 0x20>;
135 interrupts = <1 14 0xf04>;
142 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
143 <0 18 IRQ_TYPE_LEVEL_HIGH>,
144 <0 19 IRQ_TYPE_LEVEL_HIGH>,
145 <0 20 IRQ_TYPE_LEVEL_HIGH>;
167 #clock-cells = <0>;
174 #clock-cells = <0>;
179 #clock-cells = <0>;
187 #clock-cells = <0>;
195 #clock-cells = <0>;
203 #clock-cells = <0>;
211 #clock-cells = <0>;
219 #clock-cells = <0>;
227 pclk: pclk@0 {
228 #clock-cells = <0>;
230 clock-frequency = <0>;
236 reg = <0x40000000 0x04000000>;
246 reg = <0x44000000 0x04000000>;
256 #size-cells = <0>;
260 #size-cells = <0>;
262 port@0 {
263 reg = <0>;
305 reg = <0x10000000 0x1000>;
309 offset = <0x08>;
310 mask = <0x01>;
311 label = "versatile:0";
317 offset = <0x08>;
318 mask = <0x02>;
325 offset = <0x08>;
326 mask = <0x04>;
333 offset = <0x08>;
334 mask = <0x08>;
341 offset = <0x08>;
342 mask = <0x10>;
349 offset = <0x08>;
350 mask = <0x20>;
357 offset = <0x08>;
358 mask = <0x40>;
364 offset = <0x08>;
365 mask = <0x80>;
370 oscclk0: osc0@0c {
372 #clock-cells = <0>;
373 lock-offset = <0x20>;
374 vco-offset = <0x0C>;
379 #clock-cells = <0>;
380 lock-offset = <0x20>;
381 vco-offset = <0x10>;
386 #clock-cells = <0>;
387 lock-offset = <0x20>;
388 vco-offset = <0x14>;
393 #clock-cells = <0>;
394 lock-offset = <0x20>;
395 vco-offset = <0x18>;
400 #clock-cells = <0>;
401 lock-offset = <0x20>;
402 vco-offset = <0x1c>;
407 #clock-cells = <0>;
408 lock-offset = <0x20>;
409 vco-offset = <0xd4>;
414 #clock-cells = <0>;
415 lock-offset = <0x20>;
416 vco-offset = <0xd8>;
423 reg = <0x10001000 0x1000>;
431 assigned-clocks = <&sp810_syscon 0>,
443 #size-cells = <0>;
445 reg = <0x10002000 0x1000>;
449 reg = <0x68>;
455 reg = <0x10004000 0x1000>;
457 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
464 reg = <0x10005000 0x1000>;
466 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>,
467 <0 15 IRQ_TYPE_LEVEL_HIGH>;
476 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
482 reg = <0x10006000 0x1000>;
484 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
491 reg = <0x10007000 0x1000>;
493 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
500 reg = <0x10009000 0x1000>;
502 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
509 reg = <0x1000a000 0x1000>;
511 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
518 reg = <0x1000b000 0x1000>;
520 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
527 reg = <0x1000c000 0x1000>;
529 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
536 reg = <0x1000d000 0x1000>;
538 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
545 reg = <0x1000f000 0x1000>;
547 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
555 reg = <0x10010000 0x1000>;
557 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
564 reg = <0x10011000 0x1000>;
566 interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>;
568 clocks = <&sp810_syscon 0>,
578 reg = <0x10012000 0x1000>;
580 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
592 reg = <0x10013000 0x1000>;
595 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
605 reg = <0x10014000 0x1000>;
608 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
618 reg = <0x10015000 0x1000>;
621 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
631 #size-cells = <0>;
633 reg = <0x10016000 0x1000>;
638 reg = <0x10017000 0x1000>;
640 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
647 reg = <0x10018000 0x1000>;
655 reg = <0x10019000 0x1000>;
664 reg = <0x10020000 0x1000>;
667 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
676 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
690 reg = <0x1e001000 0x1000>,
691 <0x1e000000 0x100>;
693 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
699 reg = <0x4e000000 0x10000>;
701 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
712 reg = <0x4f000000 0x20000>;
714 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;