Lines Matching +full:gic +full:- +full:400
1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/mt7629-clk.h>
11 #include <dt-bindings/power/mt7622-power.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/reset/mt7629-resets.h>
18 interrupt-parent = <&sysirq>;
19 #address-cells = <1>;
20 #size-cells = <1>;
23 #address-cells = <1>;
24 #size-cells = <0>;
25 enable-method = "mediatek,mt6589-smp";
29 compatible = "arm,cortex-a7";
31 clock-frequency = <1250000000>;
32 cci-control-port = <&cci_control2>;
37 compatible = "arm,cortex-a7";
39 clock-frequency = <1250000000>;
40 cci-control-port = <&cci_control2>;
45 compatible = "arm,cortex-a7-pmu";
48 interrupt-affinity = <&cpu0>, <&cpu1>;
51 clk20m: oscillator-0 {
52 compatible = "fixed-clock";
53 #clock-cells = <0>;
54 clock-frequency = <20000000>;
55 clock-output-names = "clk20m";
58 clk40m: oscillator-1 {
59 compatible = "fixed-clock";
60 #clock-cells = <0>;
61 clock-frequency = <40000000>;
62 clock-output-names = "clkxtal";
66 compatible = "arm,armv7-timer";
67 interrupt-parent = <&gic>;
72 clock-frequency = <20000000>;
76 compatible = "simple-bus";
77 #address-cells = <1>;
78 #size-cells = <1>;
82 compatible = "mediatek,mt7629-infracfg", "syscon";
84 #clock-cells = <1>;
88 compatible = "mediatek,mt7629-pericfg", "syscon";
90 #clock-cells = <1>;
93 scpsys: power-controller@10006000 {
94 compatible = "mediatek,mt7629-scpsys",
95 "mediatek,mt7622-scpsys";
96 #power-domain-cells = <1>;
99 clock-names = "hif_sel";
100 assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>;
101 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
106 compatible = "mediatek,mt7629-timer",
107 "mediatek,mt6765-timer";
112 clock-names = "clk20m";
115 sysirq: interrupt-controller@10200a80 {
116 compatible = "mediatek,mt7629-sysirq",
117 "mediatek,mt6577-sysirq";
119 interrupt-controller;
120 #interrupt-cells = <3>;
121 interrupt-parent = <&gic>;
125 compatible = "mediatek,mt7629-apmixedsys", "syscon";
127 #clock-cells = <1>;
131 compatible = "mediatek,mt7629-rng",
132 "mediatek,mt7623-rng";
135 clock-names = "rng";
139 compatible = "mediatek,mt7629-topckgen", "syscon";
141 #clock-cells = <1>;
145 compatible = "mediatek,mt7629-wdt",
146 "mediatek,mt6589-wdt";
151 compatible = "mediatek,mt7629-pinctrl";
154 reg-names = "base", "eint";
155 gpio-controller;
156 gpio-ranges = <&pio 0 0 79>;
157 #gpio-cells = <2>;
158 #interrupt-cells = <2>;
159 interrupt-controller;
161 interrupt-parent = <&gic>;
164 gic: interrupt-controller@10300000 { label
165 compatible = "arm,gic-400";
166 interrupt-controller;
167 #interrupt-cells = <3>;
168 interrupt-parent = <&gic>;
176 compatible = "arm,cci-400";
177 #address-cells = <1>;
178 #size-cells = <1>;
182 cci_control0: slave-if@1000 {
183 compatible = "arm,cci-400-ctrl-if";
184 interface-type = "ace-lite";
188 cci_control1: slave-if@4000 {
189 compatible = "arm,cci-400-ctrl-if";
190 interface-type = "ace";
194 cci_control2: slave-if@5000 {
195 compatible = "arm,cci-400-ctrl-if";
196 interface-type = "ace";
201 compatible = "arm,cci-400-pmu,r1";
212 compatible = "mediatek,mt7629-uart",
213 "mediatek,mt6577-uart";
218 clock-names = "baud", "bus";
223 compatible = "mediatek,mt7629-uart",
224 "mediatek,mt6577-uart";
229 clock-names = "baud", "bus";
234 compatible = "mediatek,mt7629-uart",
235 "mediatek,mt6577-uart";
240 clock-names = "baud", "bus";
245 compatible = "mediatek,mt7629-pwm";
247 #pwm-cells = <2>;
251 clock-names = "top", "main", "pwm1";
252 assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
253 assigned-clock-parents =
259 compatible = "mediatek,mt7629-i2c",
260 "mediatek,mt2712-i2c";
264 clock-div = <4>;
267 clock-names = "main", "dma";
268 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
269 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
270 #address-cells = <1>;
271 #size-cells = <0>;
276 compatible = "mediatek,mt7629-spi",
277 "mediatek,mt7622-spi";
278 #address-cells = <1>;
279 #size-cells = <0>;
285 clock-names = "parent-clk", "sel-clk", "spi-clk";
290 compatible = "mediatek,mt7629-nor",
291 "mediatek,mt8173-nor";
295 clock-names = "spi", "sf";
296 #address-cells = <1>;
297 #size-cells = <0>;
302 compatible = "mediatek,mt7629-ssusbsys", "syscon";
304 #clock-cells = <1>;
305 #reset-cells = <1>;
309 compatible = "mediatek,mt7629-xhci",
310 "mediatek,mtk-xhci";
313 reg-names = "mac", "ippc";
319 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
320 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
323 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
326 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
332 u3phy0: usb-phy@1a0c4000 {
333 compatible = "mediatek,generic-tphy-v2";
334 #address-cells = <1>;
335 #size-cells = <1>;
339 u2port0: usb-phy@0 {
342 clock-names = "ref";
343 #phy-cells = <1>;
347 u3port0: usb-phy@700 {
350 clock-names = "ref";
351 #phy-cells = <1>;
357 compatible = "mediatek,mt7629-pciesys", "syscon";
359 #clock-cells = <1>;
360 #reset-cells = <1>;
364 compatible = "mediatek,mt7629-pcie";
368 reg-names = "subsys","port1";
369 #address-cells = <3>;
370 #size-cells = <2>;
379 clock-names = "sys_ck1", "ahb_ck1",
382 assigned-clocks = <&topckgen CLK_TOP_SATA_SEL>,
385 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL2_D4>,
389 phy-names = "pcie-phy1";
390 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
391 bus-range = <0x00 0xff>;
397 #address-cells = <3>;
398 #size-cells = <2>;
399 #interrupt-cells = <1>;
401 num-lanes = <1>;
402 interrupt-map-mask = <0 0 0 7>;
403 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
408 pcie_intc1: interrupt-controller {
409 interrupt-controller;
410 #address-cells = <0>;
411 #interrupt-cells = <1>;
416 pciephy1: pcie-phy@1a14a000 {
417 compatible = "mediatek,generic-tphy-v2";
418 #address-cells = <1>;
419 #size-cells = <1>;
426 clock-names = "ref";
427 #phy-cells = <1>;
433 compatible = "mediatek,mt7629-ethsys", "syscon";
435 #clock-cells = <1>;
436 #reset-cells = <1>;
440 compatible = "mediatek,mt7629-eth","syscon";
462 clock-names = "ethif", "sgmiitop", "esw", "gp0", "gp1",
468 assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>,
470 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
472 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
476 #address-cells = <1>;
477 #size-cells = <0>;
482 compatible = "mediatek,mt7629-sgmiisys", "syscon";
484 #clock-cells = <1>;
488 compatible = "mediatek,mt7629-sgmiisys", "syscon";
490 #clock-cells = <1>;