Lines Matching +full:mmu +full:- +full:500
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/omap.h>
12 #include <dt-bindings/clock/omap5.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 interrupt-parent = <&wakeupgen>;
44 #address-cells = <1>;
45 #size-cells = <0>;
49 compatible = "arm,cortex-a15";
52 operating-points = <
59 clock-names = "cpu";
61 clock-latency = <300000>; /* From omap-cpufreq driver */
64 #cooling-cells = <2>; /* min followed by max */
68 compatible = "arm,cortex-a15";
71 operating-points = <
78 clock-names = "cpu";
80 clock-latency = <300000>; /* From omap-cpufreq driver */
83 #cooling-cells = <2>; /* min followed by max */
87 thermal-zones {
88 #include "omap4-cpu-thermal.dtsi"
89 #include "omap5-gpu-thermal.dtsi"
90 #include "omap5-core-thermal.dtsi"
94 compatible = "arm,armv7-timer";
100 interrupt-parent = <&gic>;
104 compatible = "arm,cortex-a15-pmu";
109 gic: interrupt-controller@48211000 {
110 compatible = "arm,cortex-a15-gic";
111 interrupt-controller;
112 #interrupt-cells = <3>;
117 interrupt-parent = <&gic>;
120 wakeupgen: interrupt-controller@48281000 {
121 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
122 interrupt-controller;
123 #interrupt-cells = <3>;
125 interrupt-parent = <&gic>;
133 compatible = "ti,omap-infra";
135 compatible = "ti,omap4-mpu";
149 compatible = "ti,omap5-l3-noc", "simple-bus";
150 #address-cells = <1>;
151 #size-cells = <1>;
153 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
174 compatible = "mmio-sram";
179 compatible = "ti,omap4430-gpmc";
181 #address-cells = <2>;
182 #size-cells = <1>;
185 dma-names = "rxtx";
186 gpmc,num-cs = <8>;
187 gpmc,num-waitpins = <4>;
190 clock-names = "fck";
191 interrupt-controller;
192 #interrupt-cells = <2>;
193 gpio-controller;
194 #gpio-cells = <2>;
197 target-module@55082000 {
198 compatible = "ti,sysc-omap2", "ti,sysc";
202 reg-names = "rev", "sysc", "syss";
203 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
206 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
210 clock-names = "fck";
212 reset-names = "rstctrl";
214 #size-cells = <1>;
215 #address-cells = <1>;
217 mmu_ipu: mmu@0 {
218 compatible = "ti,omap4-iommu";
221 #iommu-cells = <0>;
222 ti,iommu-bus-err-back;
227 compatible = "ti,omap5-dsp";
232 firmware-name = "omap5-dsp-fw.xe64T";
238 compatible = "ti,omap5-ipu";
240 reg-names = "l2ram";
244 firmware-name = "omap5-ipu-fw.xem4";
250 compatible = "ti,omap5-dmm";
257 compatible = "ti,emif-4d5";
259 ti,no-idle-on-init;
260 phy-type = <2>; /* DDR PHY type: Intelli PHY */
263 hw-caps-read-idle-ctrl;
264 hw-caps-ll-interface;
265 hw-caps-temp-alert;
269 compatible = "ti,emif-4d5";
271 ti,no-idle-on-init;
272 phy-type = <2>; /* DDR PHY type: Intelli PHY */
275 hw-caps-read-idle-ctrl;
276 hw-caps-ll-interface;
277 hw-caps-temp-alert;
280 aes1_target: target-module@4b501000 {
281 compatible = "ti,sysc-omap2", "ti,sysc";
285 reg-names = "rev", "sysc", "syss";
286 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
288 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
292 ti,syss-mask = <1>;
295 clock-names = "fck";
296 #address-cells = <1>;
297 #size-cells = <1>;
301 compatible = "ti,omap4-aes";
305 dma-names = "tx", "rx";
309 aes2_target: target-module@4b701000 {
310 compatible = "ti,sysc-omap2", "ti,sysc";
314 reg-names = "rev", "sysc", "syss";
315 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
317 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
321 ti,syss-mask = <1>;
324 clock-names = "fck";
325 #address-cells = <1>;
326 #size-cells = <1>;
330 compatible = "ti,omap4-aes";
334 dma-names = "tx", "rx";
338 sham_target: target-module@4b100000 {
339 compatible = "ti,sysc-omap3-sham", "ti,sysc";
343 reg-names = "rev", "sysc", "syss";
344 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
346 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
349 ti,syss-mask = <1>;
352 clock-names = "fck";
353 #address-cells = <1>;
354 #size-cells = <1>;
358 compatible = "ti,omap4-sham";
362 dma-names = "rx";
372 compatible = "ti,omap5430-bandgap";
374 #thermal-sensor-cells = <1>;
379 compatible = "snps,dwc-ahci";
383 phy-names = "sata-phy";
386 ports-implemented = <0x1>;
389 target-module@56000000 {
390 compatible = "ti,sysc-omap4", "ti,sysc";
393 reg-names = "rev", "sysc";
394 ti,sysc-midle = <SYSC_IDLE_FORCE>,
397 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
401 clock-names = "fck";
402 #address-cells = <1>;
403 #size-cells = <1>;
412 target-module@58000000 {
413 compatible = "ti,sysc-omap2", "ti,sysc";
416 reg-names = "rev", "syss";
417 ti,syss-mask = <1>;
422 clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
423 #address-cells = <1>;
424 #size-cells = <1>;
428 compatible = "ti,omap5-dss";
432 clock-names = "fck";
433 #address-cells = <1>;
434 #size-cells = <1>;
437 target-module@1000 {
438 compatible = "ti,sysc-omap2", "ti,sysc";
442 reg-names = "rev", "sysc", "syss";
443 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
446 ti,sysc-midle = <SYSC_IDLE_FORCE>,
449 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
453 ti,syss-mask = <1>;
455 clock-names = "fck";
456 #address-cells = <1>;
457 #size-cells = <1>;
461 compatible = "ti,omap5-dispc";
465 clock-names = "fck";
469 target-module@2000 {
470 compatible = "ti,sysc-omap2", "ti,sysc";
474 reg-names = "rev", "sysc", "syss";
475 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
478 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
480 ti,syss-mask = <1>;
482 clock-names = "fck";
483 #address-cells = <1>;
484 #size-cells = <1>;
488 compatible = "ti,omap5-rfbi";
492 clock-names = "fck", "ick";
496 target-module@4000 {
497 compatible = "ti,sysc-omap2", "ti,sysc";
501 reg-names = "rev", "sysc", "syss";
502 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
505 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
509 ti,syss-mask = <1>;
510 #address-cells = <1>;
511 #size-cells = <1>;
515 compatible = "ti,omap5-dsi";
519 reg-names = "proto", "phy", "pll";
524 clock-names = "fck", "sys_clk";
528 target-module@9000 {
529 compatible = "ti,sysc-omap2", "ti,sysc";
533 reg-names = "rev", "sysc", "syss";
534 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
537 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
541 ti,syss-mask = <1>;
542 #address-cells = <1>;
543 #size-cells = <1>;
547 compatible = "ti,omap5-dsi";
551 reg-names = "proto", "phy", "pll";
556 clock-names = "fck", "sys_clk";
560 target-module@40000 {
561 compatible = "ti,sysc-omap4", "ti,sysc";
564 reg-names = "rev", "sysc";
565 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
569 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
572 clock-names = "fck", "dss_clk";
573 #address-cells = <1>;
574 #size-cells = <1>;
578 compatible = "ti,omap5-hdmi";
583 reg-names = "wp", "pll", "phy", "core";
588 clock-names = "fck", "sys_clk";
590 dma-names = "audio_tx";
596 abb_mpu: regulator-abb-mpu {
597 compatible = "ti,abb-v2";
598 regulator-name = "abb_mpu";
599 #address-cells = <0>;
600 #size-cells = <0>;
602 ti,settling-time = <50>;
603 ti,clock-cycles = <16>;
607 reg-names = "base-address", "int-address",
608 "efuse-address", "ldo-address";
609 ti,tranxdone-status-mask = <0x80>;
611 ti,ldovbb-override-mask = <0x400>;
613 ti,ldovbb-vset-mask = <0x1F>;
626 abb_mm: regulator-abb-mm {
627 compatible = "ti,abb-v2";
628 regulator-name = "abb_mm";
629 #address-cells = <0>;
630 #size-cells = <0>;
632 ti,settling-time = <50>;
633 ti,clock-cycles = <16>;
637 reg-names = "base-address", "int-address",
638 "efuse-address", "ldo-address";
639 ti,tranxdone-status-mask = <0x80000000>;
641 ti,ldovbb-override-mask = <0x400>;
643 ti,ldovbb-vset-mask = <0x1F>;
659 polling-delay = <500>; /* milliseconds */
660 coefficients = <65 (-1791)>;
663 #include "omap5-l4.dtsi"
664 #include "omap54xx-clocks.dtsi"
667 coefficients = <117 (-2992)>;
674 #include "omap5-l4-abe.dtsi"
675 #include "omap54xx-clocks.dtsi"
679 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
681 #reset-cells = <1>;
684 prm_abe: prm@500 {
685 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
687 #power-domain-cells = <0>;
691 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
693 #reset-cells = <1>;
697 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
699 #reset-cells = <1>;
703 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
705 #reset-cells = <1>;
709 /* Preferred always-on timer for clockevent */
711 ti,no-reset-on-init;
712 ti,no-idle;
714 assigned-clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>;
715 assigned-clock-parents = <&sys_32k_ck>;