Lines Matching +full:0 +full:x2c004000
16 arm,hbi = <0x249>;
17 arm,vexpress,site = <0xf>;
36 #size-cells = <0>;
38 cpu0: cpu@0 {
41 reg = <0>;
61 reg = <0x100>;
71 reg = <0x101>;
81 reg = <0x102>;
109 reg = <0 0x80000000 0 0x40000000>;
117 /* Chipselect 2 is physically at 0x18000000 */
121 reg = <0 0x18000000 0 0x00800000>;
128 reg = <0 0x2a490000 0 0x1000>;
129 interrupts = <0 98 4>;
136 reg = <0 0x2b000000 0 0x1000>;
137 interrupts = <0 85 4>;
144 reg = <0 0x2b0a0000 0 0x1000>;
152 #address-cells = <0>;
154 reg = <0 0x2c001000 0 0x1000>,
155 <0 0x2c002000 0 0x2000>,
156 <0 0x2c004000 0 0x2000>,
157 <0 0x2c006000 0 0x2000>;
158 interrupts = <1 9 0xf04>;
165 reg = <0 0x2c090000 0 0x1000>;
166 ranges = <0x0 0x0 0x2c090000 0x10000>;
171 reg = <0x4000 0x1000>;
177 reg = <0x5000 0x1000>;
182 reg = <0x9000 0x5000>;
183 interrupts = <0 105 4>,
184 <0 101 4>,
185 <0 102 4>,
186 <0 103 4>,
187 <0 104 4>;
193 reg = <0 0x7ffd0000 0 0x1000>;
194 interrupts = <0 86 4>,
195 <0 87 4>;
202 reg = <0 0x7ff00000 0 0x1000>;
203 interrupts = <0 92 4>,
204 <0 88 4>,
205 <0 89 4>,
206 <0 90 4>,
207 <0 91 4>;
214 reg = <0 0x7fff0000 0 0x1000>;
215 interrupts = <0 95 4>;
220 interrupts = <1 13 0xf08>,
221 <1 14 0xf08>,
222 <1 11 0xf08>,
223 <1 10 0xf08>;
228 interrupts = <0 68 4>,
229 <0 69 4>;
236 interrupts = <0 128 4>,
237 <0 129 4>,
238 <0 130 4>;
247 #clock-cells = <0>;
257 /* A15 PLL 0 reference clock */
259 arm,vexpress-sysreg,func = <1 0>;
261 #clock-cells = <0>;
270 #clock-cells = <0>;
275 /* A7 PLL 0 reference clock */
279 #clock-cells = <0>;
288 #clock-cells = <0>;
297 #clock-cells = <0>;
306 #clock-cells = <0>;
315 #clock-cells = <0>;
324 #clock-cells = <0>;
333 #clock-cells = <0>;
340 arm,vexpress-sysreg,func = <2 0>;
362 arm,vexpress-sysreg,func = <3 0>;
376 arm,vexpress-sysreg,func = <4 0>;
383 arm,vexpress-sysreg,func = <12 0>;
397 arm,vexpress-sysreg,func = <13 0>, <13 1>;
411 reg = <0 0x20010000 0 0x1000>;
426 reg = <0 0x20030000 0 0x1000>;
447 #size-cells = <0>;
449 port@0 {
450 reg = <0>;
475 reg = <0 0x20040000 0 0x1000>;
490 #size-cells = <0>;
492 port@0 {
493 reg = <0>;
533 reg = <0 0x2201c000 0 0x1000>;
549 reg = <0 0x2201d000 0 0x1000>;
565 reg = <0 0x2203c000 0 0x1000>;
581 reg = <0 0x2203d000 0 0x1000>;
597 reg = <0 0x2203e000 0 0x1000>;
616 ranges = <0 0 0 0x08000000 0x04000000>,
617 <1 0 0 0x14000000 0x04000000>,
618 <2 0 0 0x18000000 0x04000000>,
619 <3 0 0 0x1c000000 0x04000000>,
620 <4 0 0 0x0c000000 0x04000000>,
621 <5 0 0 0x10000000 0x04000000>;
624 interrupt-map-mask = <0 0 63>;
625 interrupt-map = <0 0 0 &gic 0 0 4>,
626 <0 0 1 &gic 0 1 4>,
627 <0 0 2 &gic 0 2 4>,
628 <0 0 3 &gic 0 3 4>,
629 <0 0 4 &gic 0 4 4>,
630 <0 0 5 &gic 0 5 4>,
631 <0 0 6 &gic 0 6 4>,
632 <0 0 7 &gic 0 7 4>,
633 <0 0 8 &gic 0 8 4>,
634 <0 0 9 &gic 0 9 4>,
635 <0 0 10 &gic 0 10 4>,
636 <0 0 11 &gic 0 11 4>,
637 <0 0 12 &gic 0 12 4>,
638 <0 0 13 &gic 0 13 4>,
639 <0 0 14 &gic 0 14 4>,
640 <0 0 15 &gic 0 15 4>,
641 <0 0 16 &gic 0 16 4>,
642 <0 0 17 &gic 0 17 4>,
643 <0 0 18 &gic 0 18 4>,
644 <0 0 19 &gic 0 19 4>,
645 <0 0 20 &gic 0 20 4>,
646 <0 0 21 &gic 0 21 4>,
647 <0 0 22 &gic 0 22 4>,
648 <0 0 23 &gic 0 23 4>,
649 <0 0 24 &gic 0 24 4>,
650 <0 0 25 &gic 0 25 4>,
651 <0 0 26 &gic 0 26 4>,
652 <0 0 27 &gic 0 27 4>,
653 <0 0 28 &gic 0 28 4>,
654 <0 0 29 &gic 0 29 4>,
655 <0 0 30 &gic 0 30 4>,
656 <0 0 31 &gic 0 31 4>,
657 <0 0 32 &gic 0 32 4>,
658 <0 0 33 &gic 0 33 4>,
659 <0 0 34 &gic 0 34 4>,
660 <0 0 35 &gic 0 35 4>,
661 <0 0 36 &gic 0 36 4>,
662 <0 0 37 &gic 0 37 4>,
663 <0 0 38 &gic 0 38 4>,
664 <0 0 39 &gic 0 39 4>,
665 <0 0 40 &gic 0 40 4>,
666 <0 0 41 &gic 0 41 4>,
667 <0 0 42 &gic 0 42 4>;
674 ranges = <0 0 0x40000000 0x3fef0000>;
676 interrupt-map-mask = <0 3>;
677 interrupt-map = <0 0 &gic 0 36 4>,
678 <0 1 &gic 0 37 4>,
679 <0 2 &gic 0 38 4>,
680 <0 3 &gic 0 39 4>;